• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 19 matches

• 2007
• 
  Susmit Biswas, Frederic T. Chong, Tzvetan S. Metodi, Ryan Kastner:
  A pageable, defect-tolerant nanoscale memory system. NANOARCH 2007: 85-92
• 
  Jianwei Dai, Lei Wang, Faquir C. Jain:
  Analysis of defect tolerance in molecular electronics using information-theoretic measures. NANOARCH 2007: 21-26
• 
  Shamik Das, Matthew F. Bauwens:
  Clocking nanocircuits for nanocomputers and other nanoelectronic systems. NANOARCH 2007: 123-128
• 
  Masoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi:
  Robust self-assembly of interconnects by parallel DNA growth. NANOARCH 2007: 70-76
• 
  Dennis Huo, Qiaoyan Yu, Paul Ampadu:
  A ballistic nanoelectronic device simulator. NANOARCH 2007: 38-45
• 
  Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi:
  A fast, numerical circuit-level model of carbon nanotube transistor. NANOARCH 2007: 33-37
• 
  Kyosun Kim, Ramesh Karri, Alex Orailoglu:
  Design automation for hybrid CMOS-nonoelectronics crossbars. NANOARCH 2007: 27-32
• 
  Hua Li, Joseph L. Mundy, William R. Patterson, Dimitrios Kazazis, Alexander Zaslavsky, R. Iris Bahar:
  Thermally-induced soft errors in nanoscale CMOS circuits. NANOARCH 2007: 62-69
• 
  Tzvetan S. Metodi, Andrew W. Cross, Darshan D. Thaker, Isaac L. Chuang, Frederic T. Chong:
  Design-space exploration of fault-tolerant building blocks for large-scale quantum computing. NANOARCH 2007: 7-14
• 
  Tamer Mohamed, Graham A. Jullien, Wael M. Badawy:
  Crossbar latch-based combinational and sequential logic for nano FPGA. NANOARCH 2007: 117-122
• 
  Drew C. Ness, Christian J. Hescott, David J. Lilja:
  Improving nanoelectronic designs using a statistical approach to identify key parameters in circuit level SEU simulations. NANOARCH 2007: 46-53
• 
  Ashish Kumar Singh, Hady Ali Zeineddine, Adnan Aziz, Sriram Vishwanath, Michael Orshansky:
  A heterogeneous CMOS-CNT architecture utilizing novel coding of boolean functions. NANOARCH 2007: 15-20
• 
  Dmitri B. Strukov, Konstantin K. Likharev:
  Prospects for the development of digital CMOL circuits. NANOARCH 2007: 109-116
• 
  Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo:
  A shift-register-based QCA memory architecture. NANOARCH 2007: 54-61
• 
  Girish Venkatasubramanian, P. Oscar Boykin, Renato J. O. Figueiredo:
  Design of high-yield defect-tolerant self-assembled nanoscale memories. NANOARCH 2007: 77-84
• 
  Shuo Wang, Lei Wang, Faquir C. Jain:
  Dynamic redundancy allocation for reliable and high-performance nanocomputing. NANOARCH 2007: 1-6
• 
  Teng Wang, Pritish Narayanan, Csaba Andras Moritz:
  Combining 2-level logic families in grid-based nanoscale fabrics. NANOARCH 2007: 101-108
• 
  Zhengfei Wang, Huaixiu Zheng, Qinwei Shi, Jie Chen:
  Emerging nanocircuit paradigm: Graphene-based electronics for nanoscale computing. NANOARCH 2007: 93-100
• 
  2007 IEEE International Symposium on Nanoscale Architectures, NANOARCH 2007, San Jose, CA, USA, October 21-22, 2007. IEEE Computer Society 2007, ISBN 978-1-4244-1790-2 [contents]