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Publication search results
found 45 matches
- 2011
- Ahmed H. Abdel-Gawad, Mithuna Thottethodi:
TransCom: transforming stream communication for load balance and efficiency in networks-on-chip. MICRO 2011: 237-247 - Konstantinos Aisopos, Li-Shiuan Peh:
A systematic methodology to develop resilient cache coherence protocols. MICRO 2011: 47-58 - Jesse G. Beu, Michel C. Rosier, Thomas M. Conte:
Manager-client pairing: a framework for implementing coherence hierarchies. MICRO 2011: 226-236 - Ryan Cochran, Can Hankendi, Ayse K. Coskun, Sherief Reda:
Pack & Cap: adaptive DVFS and thread packing under power caps. MICRO 2011: 175-185 - Gregory Frederick Diamos, Benjamin Ashbaugh, Subramaniam Maiyuran, Andrew Kerr, Haicheng Wu, Sudhakar Yalamanchili:
SIMD re-convergence at thread frontiers. MICRO 2011: 477-488 - Eiman Ebrahimi, Rustam Miftakhutdinov, Chris Fallin, Chang Joo Lee, José A. Joao, Onur Mutlu, Yale N. Patt:
Parallel application memory scheduling. MICRO 2011: 362-373 - Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott A. Mahlke, David I. August:
Encore: low-cost, fine-grained transient fault recovery. MICRO 2011: 398-409 - Michael Ferdman, Cansu Kaynak, Babak Falsafi:
Proactive instruction fetch. MICRO 2011: 152-162 - Nikos Foutris, Dimitris Gizopoulos, Mihalis Psarakis, Xavier Vera, Antonio González:
Accelerating microprocessor silicon validation by exposing ISA diversity. MICRO 2011: 386-397 - Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt:
Hardware transactional memory for GPU architectures. MICRO 2011: 296-307 - Mark Gebhart, Stephen W. Keckler, William J. Dally:
A compile-time managed multi-level register file hierarchy. MICRO 2011: 465-476 - Qing Guo, Xiaochen Guo, Yuxin Bai, Engin Ipek:
A resistive TCAM accelerator for data-intensive computing. MICRO 2011: 339-350 - Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke, David I. August:
Bundled execution of recurring traces for energy-efficient general purpose processing. MICRO 2011: 12-23 - Gagan Gupta, Gurindar S. Sohi:
Dataflow execution of sequential imperative programs on multicore architectures. MICRO 2011: 59-70 - Andrew W. Hay, Karin Strauss, Timothy Sherwood, Gabriel H. Loh, Doug Burger:
Preventing PCM banks from seizing too much power. MICRO 2011: 186-195 - Mitchell Hayenga, Mikko H. Lipasti:
The NoX router. MICRO 2011: 36-46 - Nikolas Ioannou, Marcelo Cintra:
Complementing user-level coarse-grain parallelism with implicit speculative parallelism. MICRO 2011: 284-295 - Seongwook Jin, Jeongseob Ahn, Sanghoon Cha, Jaehyuk Huh:
Architectural support for secure virtualization under a vulnerable hypervisor. MICRO 2011: 272-283 - Dimitris Kaseridis, Jeffrey Stuecheli, Lizy Kurian John:
Minimalist open-page: a DRAM page-mode scheduling policy for the many-core era. MICRO 2011: 24-35 - Soontae Kim, Jongmin Lee, Jesung Kim, Seokin Hong:
Residue cache: a low-energy low-area L2 cache architecture via compression and partial hits. MICRO 2011: 420-429 - Tushar Krishna, Li-Shiuan Peh, Bradford M. Beckmann, Steven K. Reinhardt:
Towards the ideal on-chip fabric for 1-to-many and many-to-1 communication. MICRO 2011: 71-82 - Marc de Kruijf, Karthikeyan Sankaralingam:
Idempotent processor architecture. MICRO 2011: 140-151 - Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter:
Active management of timing guardband to save energy in POWER7. MICRO 2011: 1-11 - Sheng Li, Kevin T. Lim, Paolo Faraboschi, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi:
System-level integrated server architectures for scale-out datacenters. MICRO 2011: 260-271 - Gabriel H. Loh:
A register-file approach for row buffer caches in die-stacked DRAMs. MICRO 2011: 351-361 - Gabriel H. Loh, Mark D. Hill:
Efficiently enabling conventional block sizes for very large die-stacked DRAM caches. MICRO 2011: 454-464 - Jason Mars, Lingjia Tang, Robert Hundt, Kevin Skadron, Mary Lou Soffa:
Bubble-Up: increasing utilization in modern warehouse scale computers via sensible co-locations. MICRO 2011: 248-259 - George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally:
Packet chaining: efficient single-cycle allocation for on-chip networks. MICRO 2011: 83-94 - Sai Prashanth Muralidhara, Lavanya Subramanian, Onur Mutlu, Mahmut T. Kandemir, Thomas Moscibroda:
Reducing memory interference in multicore systems via application-aware memory channel partitioning. MICRO 2011: 374-385 - Veynu Narasiman, Michael Shebanow, Chang Joo Lee, Rustam Miftakhutdinov, Onur Mutlu, Yale N. Patt:
Improving GPU performance via large warps and two-level warp scheduling. MICRO 2011: 308-317
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retrieved on 2024-06-05 23:03 CEST from data curated by the dblp team
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