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Publication search results
found 46 matches
- 2018
- Salem Abdennadher, Michael Altmann, Bin Xue:
Challenges and emerging solutions in testing HBM IO & systems. LATS 2018: 1-4 - Alexander Aponte-Moreno, Alejandro Moncada, Felipe Restrepo-Calle, Cesar Augusto Pedraza:
A review of approximate computing techniques towards fault mitigation in HW/SW systems. LATS 2018: 1-6 - Fábio B. Armelin, Lírida A. B. Naviner, Roberto d'Amore:
Using FPGA self-produced transients to emulate SETs for SER estimation. LATS 2018: 1-3 - Fábio B. Armelin, Lirida A. B. Naviner, Roberto d'Amore:
Probability aware fault-injection approach for SER estimation. LATS 2018: 1-3 - Hassen Aziza, Karine Coulié, Wenceslas Rahajandraibe, Remy Vauche:
Using short-term fourier transform for particle detection and recognition in a CMOS oscillator-based chain. LATS 2018: 1-5 - Carlos L. G. Batista, Eliane Martins, Maria de Fátima Mattiello-Francisco:
On the use of a failure emulator mechanism at nanosatellite subsystems integration tests. LATS 2018: 1-6 - Thales E. Becker, Fábio Fedrizzi Vidor, Gilson I. Wirth, Thorsten Meyers, Julia Reker, Ulrich Hilleringmann:
Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors. LATS 2018: 1-6 - Fabio Benevenuti, Fernanda Lima Kastensmidt:
Reliability evaluation on interfacing with AXI and AXI-S on Xilinx Zynq-7000 AP-SoC. LATS 2018: 1-6 - Luis Alberto Contreras Benites, Fernanda Lima Kastensmidt:
Automated design flow for applying Triple Modular Redundancy (TMR) in complex digital circuits. LATS 2018: 1-4 - Riccardo Cantoro, Andrea Firrincieli, Davide Piumatti, Marco Restifo, Ernesto Sánchez, Matteo Sonza Reorda:
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications. LATS 2018: 1-6 - Paulo Vinicius Cardoso, Patrícia Pitthan Barcelos:
Validation of a dynamic checkpoint mechanism for Apache Hadoop with failure scenarios. LATS 2018: 1-6 - Dionisio de Carvalho, Bruno Sanches, M. De Carvalho, Wilhelmus A. M. Van Noije:
A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests. LATS 2018: 1-6 - Augusto Einsfeldt, Renato C. Giacomini:
Fault-tolerant architecture with full recovery under presence of SEU. LATS 2018: 1-4 - Stefano Esposito, Serhiy Avramenko, Massimo Violante:
RTOS for mixed criticality applications deployed on NoC-based COTS MPSoC. LATS 2018: 1-6 - Stefano Esposito, Jacopo Sini, Massimo Violante:
Real-time validation of mixed-criticality applications. LATS 2018: 1-6 - Moritz Fieback, Mottaqiallah Taouil, Said Hamdioui, Marco Rovatti:
Ionizing radiation modeling in DRAM transistors. LATS 2018: 1-6 - Eduardo Garcia-Espinosa, Omar Longoria-Gandara, Enrique Gonzalez-Garcia, Arturo Veloz-Guerrero:
Post-silicon validation based on synthetic test patterns for early detection of timing anomalies. LATS 2018: 1-5 - Iuri Albandes Cunha Gomes, Alejandro Serrano-Cases, Antonio J. Sanchez-Clemente, Mayler G. A. Martins, Antonio Martínez-Álvarez, Sergio Cuenca-Asensi, Fernanda Lima Kastensmidt:
Improving approximate-TMR using multi-objective optimization genetic algorithm. LATS 2018: 1-6 - Andres F. Gomez, Roberto Gómez, Víctor H. Champac:
A metric-guided gate-sizing methodology for aging guardband reduction. LATS 2018: 1-6 - Amit Karel, Florence Azaïs, Mariane Comte, Jean-Marc Gallière, Michel Renovell:
Impact of process variations on the detectability of resistive short defects: Comparative analysis between 28nm Bulk and FDSOI technologies. LATS 2018: 1-5 - Alexandra Kourfali, Dirk Stroobandt:
Superimposed in-circuit debugging for self-healing FPGA overlays. LATS 2018: 1-6 - Luiz Carlos Kretly, Ricardo Maltione, Marcelo Gradella Villalva:
A novel method of impact and failure mechanism analysis of RF-based fault injection: A frequency response analyzer, FRA. LATS 2018: 1-4 - Israel C. Lopes, Fabio Benevenuti, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Paolo Rech:
Reliability analysis on case-study traffic sign convolutional neural network on APSoC. LATS 2018: 1-6 - Rafael Melo Macieira, Edna Barros:
TDevCGen: A synthesis toolset of HW/SW communication protocol monitors from high-level specifications. LATS 2018: 1-6 - Andrea Marcelli, Ernesto Sánchez, Giovanni Squillero, Muhammad Usman Jamal, Afnan Imtiaz, Simone Machetti, Filippo Mangani, Paolo Monti, Davide Pola, Alessandro Salvato, Michele Simili:
Defeating hardware Trojan in microprocessor cores through software obfuscation. LATS 2018: 1-6 - G. Cardoso Medeiros, E. Brum, Leticia Bolzani Poehls, Thiago Copetti, Tiago R. Balen:
Influence of temperature on dynamic fault behavior due to resistive defects in FinFET-based SRAMs. LATS 2018: 1-6 - Joao de Moraes, Taisy Silva Weber, Guilherme Muller, Tiago Dall'Agnol, Rafael Macedo, Elaine P. L. Scartezzini, Roque Eduardo Dapper, Sérgio Luis Cechin, Joao Netto:
Architecture of an industrial analog input designed to meet safety requirements. LATS 2018: 1-4 - Felix Mühlbauer, Lukas Schröder, Mario Schölzel:
A fault tolerant dynamically scheduled processor with partial permanent fault handling. LATS 2018: 1-6 - Juliano Oliveira, Marcilei Aparecida Guazzelli, Marco Antonio Assis, Renato C. Giacomini:
Single event effect: Simulations and analysis on 3N163 PMOS transistor. LATS 2018: 1-3 - Ingrid F. V. Oliveira, Rafael B. Schvittz, Paulo F. Butzen:
Fault masking ratio analysis of majority voters topologies. LATS 2018: 1-6
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