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Publication search results
found 32 matches
- 2004
- Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das:
Evaluating the Imagine Stream Architecture. ISCA 2004: 14-25 - Alaa R. Alameldeen, David A. Wood:
Adaptive Cache Compression for High-Performance Processors. ISCA 2004: 212-223 - Lakshmi N. Bairavasundaram, Muthian Sivathanu, Andrea C. Arpaci-Dusseau, Remzi H. Arpaci-Dusseau:
X-RAY: A Non-Invasive Exclusive Caching Mechanism for RAIDs. ISCA 2004: 176-187 - J. Adam Butts, Gurindar S. Sohi:
Use-Based Register Caching with Decoupled Indexing. ISCA 2004: 302-313 - Harold W. Cain, Mikko H. Lipasti:
Memory Ordering: A Value-Based Approach. ISCA 2004: 90-101 - Mainak Chaudhuri, Mark A. Heinrich:
SMTp: An Architecture for Next-generation Scalable Multi-threading. ISCA 2004: 124-137 - Yuan Chou, Brian Fahs, Santosh G. Abraham:
Microarchitecture Optimizations for Exploiting Memory-Level Parallelism. ISCA 2004: 76-89 - Lieven Eeckhout, Robert H. Bell Jr., Bastiaan Stougie, Koen De Bosschere, Lizy Kurian John:
Control Flow Modeling in Statistical Simulation for Accurate and Efficient Processor Design Studies. ISCA 2004: 350-363 - Ayose Falcón, Jared Stark, Alex Ramírez, Konrad Lai, Mateo Valero:
Prophet/Critic Hybrid Branch Prediction. ISCA 2004: 250-263 - Rubén González, Adrián Cristal, Daniel Ortega, Alexander V. Veidenbaum, Mateo Valero:
A Content Aware Integer Register File Organization. ISCA 2004: 314-324 - Lance Hammond, Vicky Wong, Michael K. Chen, Brian D. Carlstrom, John D. Davis, Ben Hertzberg, Manohar K. Prabhu, Honggo Wijaya, Christos Kozyrakis, Kunle Olukotun:
Transactional Memory Coherence and Consistency. ISCA 2004: 102-113 - Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan:
TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. ISCA 2004: 114-123 - Christopher J. Hughes, Sarita V. Adve:
A Formal Approach to Frequent Energy Adaptations for Multimedia Applications. ISCA 2004: 138-149 - Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob:
Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. ISCA 2004: 364-375 - Tejas Karkhanis, James E. Smith:
A First-Order Superscalar Processor Model. ISCA 2004: 338-349 - Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic:
The Vector-Thread Architecture. ISCA 2004: 52-63 - Rakesh Kumar, Dean M. Tullsen
, Parthasarathy Ranganathan, Norman P. Jouppi, Keith I. Farkas:
Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance. ISCA 2004: 64-75 - Mikko H. Lipasti, Brian R. Mestan, Erika Gunadi:
Physical Register Inlining. ISCA 2004: 325-337 - Robert D. Mullins, Andrew West, Simon W. Moore:
Low-Latency Virtual-Channel Routers for On-Chip Networks. ISCA 2004: 188-197 - John Y. Oliver
, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong:
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ISCA 2004: 150-161 - Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam:
A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy. ISCA 2004: 376-386 - Michael D. Powell, T. N. Vijaykumar:
Exploiting Resonant Behavior to Reduce Inductive Noise. ISCA 2004: 288-301 - Valentin Puente, José A. Gregorio, Fernando Vallejo, Ramón Beivide:
Immunet: A Cheap and Robust Fault-Tolerant Packet Routing Mechanism. ISCA 2004: 198-211 - Roni Rosner, Yoav Almog, Micha Moffie, Naftali Schwartz, Avi Mendelson:
Power Awareness through Selective Dynamically Optimized Traces. ISCA 2004: 162-175 - John W. Sias, Sain-Zee Ueng, Geoff A. Kent, Ian M. Steiner, Erik M. Nystrom, Wen-mei W. Hwu:
Field-testing IMPACT EPIC research results in Itanium 2. ISCA 2004: 26-39 - Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
The Case for Lifetime Reliability-Aware Microprocessors. ISCA 2004: 276-287 - Michael B. Taylor, Walter Lee, Jason E. Miller, David Wentzlaff, Ian Bratt, Ben Greenwald, Henry Hoffmann, Paul R. Johnson, Jason Sungtae Kim, James Psota, Arvind Saraf, Nathan Shnidman, Volker Strumpen, Matthew I. Frank, Saman P. Amarasinghe, Anant Agarwal:
Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. ISCA 2004: 2-13 - T. N. Vijaykumar, Zeshan Chishti:
Wire Delay is Not a Problem for SMT (In the Near Future). ISCA 2004: 40-51 - Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt:
Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor. ISCA 2004: 264-275 - Sami Yehia, Olivier Temam:
From Sequences of Dependent Instructions to Functions: An Approach for Improving Performance without ILP or Speculation. ISCA 2004: 238-249
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