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Publication search results
found 139 matches
- 2013
- Mohamed S. Abdelfattah, Vaughn Betz:
The power of communication: Energy-efficient NOCS for FPGAS. FPL 2013: 1-8 - Motoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Defect-robust FPGA architectures for intellectual property cores in system LSI. FPL 2013: 1-7 - Abdulazim Amouri, Mehdi Baradaran Tahoori:
Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview). FPL 2013: 1-2 - Hussam Amrouch, Thomas Ebi, Josef Schneider, Sridevan Parameswaran, Jörg Henkel:
Analyzing the thermal hotspots in FPGA-based embedded systems. FPL 2013: 1-4 - Arvind Arasu, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, Ramarathnam Venkatesan:
A secure coprocessor for database applications. FPL 2013: 1-8 - Kubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss:
Hardware-accelerated regular expression matching for high-throughput text analytics. FPL 2013: 1-7 - Ali Azarian:
Pipelining computing stages in configurable multicore architectures. FPL 2013: 1-2 - Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado:
FPGA implementation of Hierarchical Enumerative Coding for locally stationary image source. FPL 2013: 1-6 - Christian Beckhoff, Alexander Wold, Anders Fritzell, Dirk Koch, Jim Tørresen:
Building partial systems with GoAhead. FPL 2013: 1 - Rodrigo Bernardo, Arley H. Salvador, Eduardo Mobilon, Luis R. Monte, Stephane Boisclair, Avrum Warshawsky:
Design and FPGA implementation of a 100 Gbit/s optical transport network processor. FPL 2013: 1-4 - Fredrik Brosser, Hui Yan Cheah, Suhaib A. Fahmy:
Iterative floating point computation using FPGA DSP blocks. FPL 2013: 1-6 - Nicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, Bogdan Popa:
Arithmetic core generation using bit heaps. FPL 2013: 1-8 - Stuart Byma, J. Gregory Steffan, Paul Chow:
NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract. FPL 2013: 1 - Davor Capalija, Tarek S. Abdelrahman:
A high-performance overlay architecture for pipelined execution of data flow graphs. FPL 2013: 1-8 - Stefano Di Carlo, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo, Pascal Trotta:
Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGAS. FPL 2013: 1-4 - Stefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Piergiorgio Lanza:
FEMIP: A high performance FPGA-based features extractor & matcher for space applications. FPL 2013: 1-4 - Stefanie Castillo, Armando Astarloa, Jesús Lázaro, Sergio Salas, Isaac Ballesteros:
SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systems. FPL 2013: 1-4 - Ediz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai:
Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfiguration. FPL 2013: 1-4 - Ren Chen, Hoang Le, Viktor K. Prasanna:
Energy efficient parameterized FFT architecture. FPL 2013: 1-7 - Yi-Chung Chen, Wei Zhang, Hai (Helen) Li:
A hardware security scheme for RRAM-based FPGA. FPL 2013: 1-4 - Chuan Cheng, Christos-Savvas Bouganis:
Accelerating Random Forest training process using FPGA. FPL 2013: 1-7 - Xiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang:
A CMOS Field Programmable Analog Array for intelligent sensory application. FPL 2013: 1-4 - Charles Chiasson, Vaughn Betz:
Should FPGAS abandon the pass-gate? FPL 2013: 1-8 - Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo:
Automated synthesis of FPGA-based heterogeneous interconnect topologies. FPL 2013: 1-8 - Anup Das, Shyamsundar Venkataraman, Akash Kumar:
Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulation. FPL 2013: 1-8 - Fangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang:
Timing-constrained minimum area/power FPGA memory mapping. FPL 2013: 1-4 - Susana Eiroa, Iluminada Baturone:
FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family. FPL 2013: 1-4 - Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt:
Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGAS. FPL 2013: 1-7 - Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele:
Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. FPL 2013: 1-8 - Shakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal:
MAMPSX: A demonstration of rapid, predictable HMPSOC synthesis. FPL 2013: 1
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