• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 57 matches

• 2017
• 
  Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet:
  A Configurable FPGA Implementation of the Tanh Function Using DCT Interpolation. FCCM 2017: 168-171
• 
  Abedalmuhdi Almomany, B. Earl Wells, Ken-ichi Nishikawa:
  Efficient Particle-Grid Space Interpolation of an FPGA-Accelerated Particle-in-Cell Plasma Simulation. FCCM 2017: 76-79
• 
  Adewale Adetomi, Godwin Enemali, Tughrul Arslan:
  Relocating Encrypted Partial Bitstreams by Advance Task Address Loading. FCCM 2017: 188-191
• 
  Ian J. Barge, Cristinel Ababei:
  A Network-on-Chip Based H.264 Video Decoder Prototype Implemented on FPGAs. FCCM 2017: 197
• 
  Edward Bartz, Jorge Chaves, Yuri Gershtein, Eva Halkiadakis, Michael D. Hildreth, Savvas Kyriacou, Kevin Lannon, Anthony Lefeld, Anders Ryd, Louise Skinnari, Robert Stone, Charles Strohman, Zhengcheng Tao, Brian Winer, Peter Wittich, Zhiru Zhang, Margaret Zientek:
  FPGA-Based Real-Time Charged Particle Trajectory Reconstruction at the Large Hadron Collider. FCCM 2017: 64-71
• 
  Young Kyu Choi, Jason Cong:
  HLScope: High-Level Performance Debugging for FPGA Designs. FCCM 2017: 125-128
• 
  Philip Colangelo, Randy Huang, Enno Lübbers, Martin Margala, Kevin Nealis:
  Fine-Grained Acceleration of Binary Neural Networks Using Intel® Xeon® Processor with Integrated FPGA. FCCM 2017: 135
• 
  Ashutosh Dhar, Deming Chen:
  Efficient GPGPU Computing with Cross-Core Resource Sharing and Core Reconfiguration. FCCM 2017: 48-55
• 
  Naveen Kumar Dumpala, Shivukumar B. Patil, Daniel E. Holcomb, Russell Tessier:
  Energy Efficient Loop Unrolling for Low-Cost FPGAs. FCCM 2017: 117-120
• 
  Shane T. Fleming, David B. Thomas:
  Using Runahead Execution to Hide Memory Latency in High Level Synthesis. FCCM 2017: 109-116
• 
  Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang:
  A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators. FCCM 2017: 227-234
• 
  Jeffrey Goeders:
  Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage Devices. FCCM 2017: 136-143
• 
  Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong:
  FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates. FCCM 2017: 152-159
• 
  Jianxin Guo, Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
  Bit-Width Based Resource Partitioning for CNN Acceleration on FPGA. FCCM 2017: 31
• 
  Jong Hun Han, Neelakandan Manihatty Bojan, Andrew W. Moore:
  Exploration of FPGA-Based Packet Switches for Rack-Scale Computers on a Board. FCCM 2017: 133
• 
  Festus Hategekimana, Christophe Bobda:
  Applying the Flask Security Architecture to Secure SoC Design. FCCM 2017: 198
• 
  Sam M. H. Ho, C.-H. Dominic Hung, Ho-Cheung Ng, Maolin Wang, Hayden Kwok-Hay So:
  A Parameterizable Activation Function Generator for FPGA-Based Neural Network Applications. FCCM 2017: 84
• 
  Chin Hau Hoo, Akash Kumar:
  ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding. FCCM 2017: 172-179
• 
  Morteza Hosseini, Rashidul Islam, Amey M. Kulkarni, Tinoosh Mohsenin:
  A Scalable FPGA-Based Accelerator for High-Throughput MCMC Algorithms. FCCM 2017: 201
• 
  Ali Jafari, Maysam Ghovanloo, Tinoosh Mohsenin:
  A Real-Time Embedded FPGA Processor for a Stand-Alone Dual-Mode Assistive Device. FCCM 2017: 199
• 
  Lana Josipovic, Philip Brisk, Paolo Ienne:
  An Out-of-Order Load-Store Queue for Spatial Computing. FCCM 2017: 134
• 
  Sang Woo Jun, Shuotao Xu, Arvind:
  Terabyte Sort on FPGA-Accelerated Flash Storage. FCCM 2017: 17-24
• 
  Nachiket Kapre:
  On Bit-Serial NoCs for FPGAs. FCCM 2017: 32-39
• 
  Nachiket Kapre:
  Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades. FCCM 2017: 40-47
• 
  Kaan Kara, Dan Alistarh, Gustavo Alonso, Onur Mutlu, Ce Zhang:
  FPGA-Accelerated Dense Linear Machine Learning: A Precision-Convergence Trade-Off. FCCM 2017: 160-167
• 
  Soroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li:
  Accelerating Large-Scale Graph Analytics with FPGA and HMC. FCCM 2017: 82
• 
  Youngsoo Kim, Hossein Shahdoost, Shrikant Jadhav, Clay S. Gloster Jr.:
  Improving the Accuracy of Arctan for Face Detection. FCCM 2017: 202
• 
  Emmanouil Kousanakis, Apostolos Dollas, Euripides Sotiriades, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos, Athanasia Papoutsi, Panagiotis C. Petrantonakis, Panayiota Poirazi, Spyridon Chavlis, George Kastellakis:
  An Architecture for the Acceleration of a Hybrid Leaky Integrate and Fire SNN on the Convey HC-2ex FPGA-Based Processor. FCCM 2017: 56-63
• 
  Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel:
  TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. FCCM 2017: 129-132
• 
  Sicheng Li, Wei Wen, Yu Wang, Song Han, Yiran Chen, Hai Li:
  An FPGA Design Framework for CNN Sparsification and Acceleration. FCCM 2017: 28

skipping 27 more matches