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ORCIDDimitris Agiakatsikas
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2020 – today
- 2024
[j5]Dimitris Agiakatsikas
, Nikos Foutris, Aitzan Sari, Vasileios Vlagkoulis, Ioanna Souvatzoglou, Mihalis Psarakis, Ruiqi Ye, John Goodacre, Mikel Luján, Maria Kastriotou, Carlo Cazzaniga, Chris Frost:
Single Event Effects Assessment of UltraScale+ MPSoC Systems Under Atmospheric Radiation. IEEE Trans. Reliab. 73(1): 771-783 (2024)- 2023
- [j4]Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis:
A Methodology for Fault-tolerant Pareto-optimal Approximate Designs of FPGA-based Accelerators. ACM Trans. Embed. Comput. Syst. 22(4): 78:1-78:31 (2023) - [c12]Ioannis Tsounis, Dimitris Agiakatsikas, Mihalis Psarakis:
Detecting Hardware Faults in Approximate Adders via Minimum Redundancy. IOLTS 2023: 1-7 - [c11]Dimitris Agiakatsikas, George Papadimitriou, Vasileios Karakostas, Dimitris Gizopoulos, Mihalis Psarakis, Camille Bélanger-Champagne, Ewart Blackmore:
Impact of Voltage Scaling on Soft Errors Susceptibility of Multicore Server CPUs. MICRO 2023: 957-971 - [i2]Dimitris Agiakatsikas, Nikos Foutris, Aitzan Sari, Vasileios Vlagkoulis, Ioanna Souvatzoglou, Mihalis Psarakis, Ruiqi Ye, John Goodacre, Mikel Luján, Maria Kastriotou, Carlo Cazzaniga, Chris Frost:
Single Event Effects Assessment of UltraScale+ MPSoC Systems under Atmospheric Radiation. CoRR abs/2303.08098 (2023) - 2022
- [c10]Ioanna Souvatzoglou, Dimitris Agiakatsikas, George Antonopoulos, Vasileios Vlagkoulis, Aitzan Sari, Athanasios Papadimitriou, Mihalis Psarakis:
The Impact of Hardware Folding on Dependability in Spaceborne FPGA-based Neural Networks. FPT 2022: 1 - [i1]Dimitris Agiakatsikas, Nikos Foutris, Aitzan Sari, Vasileios Vlagkoulis, Ioanna Souvatzoglou, Mihalis Psarakis, Mikel Luján, Maria Kastriotou, Carlo Cazzaniga:
Evaluation of Xilinx Deep Learning Processing Unit under Neutron Irradiation. CoRR abs/2206.01981 (2022)
2010 – 2019
- 2019
- [b1]Dimitris Agiakatsikas:
High-level synthesis of triple modular redundant FPGA circuits with energy efficient error recovery mechanisms. University of New South Wales, Sydney, Australia, 2019 - 2018
- [j3]Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong:
Reconfiguration Control Networks for FPGA-based TMR systems with modular error recovery. Microprocess. Microsystems 60: 86-95 (2018) - [j2]Dimitris Agiakatsikas, Ediz Cetin, Oliver Diessel:
FMER: An Energy-Efficient Error Recovery Methodology for SRAM-Based FPGA Designs. IEEE Trans. Aerosp. Electron. Syst. 54(6): 2695-2712 (2018) - [j1]Zhuoran Zhao, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ganghee Lee, Ediz Cetin, Oliver Diessel:
Fine-Grained Module-Based Error Recovery in FPGA-Based TMR Systems. ACM Trans. Reconfigurable Technol. Syst. 11(1): 4:1-4:23 (2018) - [c9]Dimitris Agiakatsikas, Ganghee Lee, Thomas Mitchell, Ediz Cetin, Oliver Diessel:
From C to Fault-Tolerant FPGA-Based Systems. FCCM 2018: 212 - 2017
- [c8]Ganghee Lee, Dimitris Agiakatsikas, Tong Wu, Ediz Cetin, Oliver Diessel:
TLegUp: A TMR Code Generation Tool for SRAM-Based FPGA Applications Using HLS. FCCM 2017: 129-132 - [c7]Lingkan Gong, Alexander Kroh, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
Reliable SEU monitoring and recovery using a programmable configuration controller. FPL 2017: 1-6 - 2016
- [c6]Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Zhuoran Zhao, Tong Wu, Ediz Cetin, Oliver Diessel, Lingkan Gong:
Reconfiguration Control Networks for TMR Systems with Module-Based Recovery. FCCM 2016: 88-91 - [c5]Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel:
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs. FPL 2016: 1-4 - [c4]Zhuoran Zhao, Dimitris Agiakatsikas, Nguyen T. H. Nguyen, Ediz Çetin, Oliver Diessel:
Fine-grained module-based error recovery in FPGA-based TMR systems. FPT 2016: 101-108 - [c3]Lingkan Gong, Tong Wu, Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Zhuoran Zhao, Ediz Cetin, Oliver Diessel:
A Programmable Configuration Controller for fault-tolerant applications. FPT 2016: 117-124 - [c2]Nguyen T. H. Nguyen, Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel:
Dynamic scheduling of voter checks in FPGA-based TMR systems. FPT 2016: 169-172 - 2014
- [c1]Aitzan Sari, Dimitris Agiakatsikas, Mihalis Psarakis:
A soft error vulnerability analysis framework for Xilinx FPGAs. FPGA 2014: 237-240
Coauthor Index
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