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Publication search results
found 205 matches
- 2024
- Kensuke Iizuka, Kohei Ito, Ryota Yasudo, Hideharu Amano:
Power Optimized Design Framework for FPGA Clusters. IPSJ Trans. Syst. LSI Des. Methodol. 17: 77-86 (2024) - Tohru Ishihara:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 17: 1 (2024) - Takehiro Kitamura, Takashi Hisakado, Osami Wada, Mahfuzul Islam:
Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups. IPSJ Trans. Syst. LSI Des. Methodol. 17: 36-43 (2024) - Tadahiro Kuroda:
Slashing IC Power and Democratizing IC Access for the Digital Age. IPSJ Trans. Syst. LSI Des. Methodol. 17: 2-6 (2024) - Shota Nakabeppu, Nobuyuki Yamasaki:
A Learning-based Control Scheme for MTJ-based Non-volatile Flip-Flops. IPSJ Trans. Syst. LSI Des. Methodol. 17: 16-35 (2024) - Ryotaro Ohara, Atsushi Fukunaga, Masakazu Taichi, Masaya Kabuto, Riku Hamabe, Masato Ikegawa, Shintaro Izumi, Hiroshi Kawaguchi:
A Case Study for Improving Performances of Deep-Learning Processor with MRAM. IPSJ Trans. Syst. LSI Des. Methodol. 17: 7-15 (2024) - Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka:
Two-layer Bottleneck Channel Track Assignment for Analog VLSI. IPSJ Trans. Syst. LSI Des. Methodol. 17: 67-76 (2024) - Hansen Wang, Dongju Li, Tsuyoshi Isshiki:
A Low-Power Reconfigurable DNN Accelerator for Instruction-Extended RISC-V. IPSJ Trans. Syst. LSI Des. Methodol. 17: 55-66 (2024) - Yuncheng Zhang, Kenichi Okada:
Design of Synthesizable Digital Phase Locked Loops. IPSJ Trans. Syst. LSI Des. Methodol. 17: 44-54 (2024) - 2023
- Kiyoharu Hamaguchi:
Parallelizing Random and SAT-based Verification Processes for Improving Toggle Coverage. IPSJ Trans. Syst. LSI Des. Methodol. 16: 45-53 (2023) - Gaku Kataoka, Masahiro Yamamoto, Masato Inagi, Shinobu Nagayama, Shin'ichi Wakabayashi:
Feature Vectors Based on Wire Width and Distance for Lithography Hotspot Detection. IPSJ Trans. Syst. LSI Des. Methodol. 16: 2-11 (2023) - Tamon Sadasue, Tsuyoshi Isshiki:
LLVM-C2RTL: C/C++ Based System Level RTL Design Framework Using LLVM Compiler Infrastructure. IPSJ Trans. Syst. LSI Des. Methodol. 16: 12-26 (2023) - Kotaro Shimamura, Takeshi Takehara, Naohiro Ikeda:
Measurement Results of Real Circuit Delay Degradation under Realistic Workload. IPSJ Trans. Syst. LSI Des. Methodol. 16: 27-34 (2023) - Atsushi Takahashi
:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 16: 1 (2023) - Ippei Tanaka, Naoyuki Miyagawa, Tomoya Kimura, Takashi Imagawa, Hiroyuki Ochi:
A CMOS-compatible Non-volatile Memory Element using Fishbone-in-cage Capacitor. IPSJ Trans. Syst. LSI Des. Methodol. 16: 35-44 (2023) - 2022
- Yasuhiro Nakahara, Yuta Masuda, Masato Kiyama, Motoki Amagasaki, Masahiro Iida:
A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep Neural Networks. IPSJ Trans. Syst. LSI Des. Methodol. 15: 16-19 (2022) - Atsushi Takahashi:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 15: 1 (2022) - Mingfei Yu, Yukio Miyasaka, Masahiro Fujita:
Parallel Scheduling Attention Mechanism: Generalization and Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 15: 2-15 (2022) - 2021
- Satoshi Ito, Hiroki Nishikawa, Xiangbo Kong, Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Energy-aware Routing of Delivery Drones under Windy Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 14: 30-39 (2021) - Yosuke Mukasa, Shu Tanaka, Nozomu Togawa:
Experimental Evaluations of Parallel Tempering on an Ising Machine. IPSJ Trans. Syst. LSI Des. Methodol. 14: 27-29 (2021) - Shinichi Nishizawa, Shih-Ting Lin, Yih-Lang Li, Hidetoshi Onodera:
Supplemental PDK for ASAP7 Using Synopsys Flow. IPSJ Trans. Syst. LSI Des. Methodol. 14: 24-26 (2021) - Tamon Sadasue, Takuya Tanaka, Ryosuke Kasahara, Arief Darmawan, Tsuyoshi Isshiki:
Scalable Hardware Architecture for fast Gradient Boosted Tree Training. IPSJ Trans. Syst. LSI Des. Methodol. 14: 11-20 (2021) - Youngsoo Shin:
Computational Lithography Using Machine Learning Models. IPSJ Trans. Syst. LSI Des. Methodol. 14: 2-10 (2021) - Atsushi Takahashi:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 14: 1 (2021) - Qiaochu Zhao, Ittetsu Taniguchi, Takao Onoye:
A Case Study on FPGA Implementation of Parts Counting Orientation Recognition Method for Industrial Vision System. IPSJ Trans. Syst. LSI Des. Methodol. 14: 21-23 (2021) - 2020
- Motoki Amagasaki, Hiroki Oyama, Yuichiro Fujishiro, Masahiro Iida, Hiroaki Yasuda, Hiroto Ito:
R-GCN Based Function Inference for Gate-level Netlist. IPSJ Trans. Syst. LSI Des. Methodol. 13: 69-71 (2020) - Yusuke Funabashi, Atsuya Shibata, Shunsuke Negoro, Ittetsu Taniguchi, Hiroyuki Tomiyama:
A Dynamic Programming Algorithm for Energy-aware Routing of Delivery Drones. IPSJ Trans. Syst. LSI Des. Methodol. 13: 65-68 (2020) - Takumi Hosaka, Shinichi Nishizawa, Ryo Kishida, Takashi Matsumoto, Kazutoshi Kobayashi:
Universal NBTI Compact Model Replicating AC Stress/Recovery from a Single-shot Long-term DC Measurement. IPSJ Trans. Syst. LSI Des. Methodol. 13: 56-64 (2020) - Ryota Ishikawa, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa:
Scalable Stochastic Number Duplicators for Accuracy-flexible Arithmetic Circuit Design. IPSJ Trans. Syst. LSI Des. Methodol. 13: 10-20 (2020) - Yukio Mitsuyama, Takashi Asada, Makio Eguchi:
Measurement of Variations in FPGAs under Various Load Conditions. IPSJ Trans. Syst. LSI Des. Methodol. 13: 39-41 (2020)
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