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Publication search results
found 16 matches
- 2023
- Ali Khakifirooz, Eduardo Anaya, Sriram Balasubrahrmanyam, Geoff Bennett, Daniel Castro, John Egler, Kuangchan Fan, Rifat Ferdous, Kartik Ganapathi, Omar Guzman, Chang-Wan Ha, Rezaul Haque, Vinaya Harish, Majid Jalalifar, Owen Jungroth, Sung-Taeg Kang, Golnaz Karbasian, Jee-Yeon Kim, Siyue Li, Aliasgar S. Madraswala, Srivijay Maddukuri, Amr Mohammed, Shanmathi Mookiah, Shashi Nagabhushan, Binh Ngo, Deep Patel, Sai Kumar Poosarla, Naveen Prabhu V, Carlos Quiroga, Shantanu Rajwade, Ahsanur Rahman, Jalpa Shah, Rohit S. Shenoy, Ebenezer Tachie-Menson, Archana Tankasala, Sandeep Krishna Thirumala, Sagar Upadhyay, Krishnasree Upadhyayula, Ashley Velasco, Nanda Kishore Babu Vemula, Bhaskar Venkataramaiah, Jiantao Zhou, Bharat Pathak, Pranav Kalavade:
A 1.67Tb, 5b/Cell Flash Memory Fabricated in 192-Layer Floating Gate 3D-NAND Technology and Featuring a 23.3Gb/mm2 Bit Density. ISSCC 2023: 400-401 - 2022
- Nithesh Naik, B. M. Zeeshan Hameed, Nilakshman Sooriyaperakasam, Shankeeth Vinayahalingam, Vathsala Patil, Komal Smriti, Janhavi Saxena, Milap J. Shah, Sufyan Ibrahim, Anshuman Singh, Hadis Karimi, Karthickeyan Naganathan, Dasharathraj K. Shetty, Bhavan Prasad Rai, Piotr Chlosta, Bhaskar K. Somani:
Transforming healthcare through a digital revolution: A review of digital healthcare technologies and solutions. Frontiers Digit. Health 4 (2022) - Preeti Bhaskar, Amit Joshi, Padmalosani Dayalan, Muddu Vinay:
Investigating the barriers and motivators to MOOCs adoption: a qualitative analysis of teacher's perspective. Int. J. Knowl. Learn. 15(2): 120-147 (2022) - 2021
- Haseen Rahman, Ankith Vinayachandran, Sibi Raj B. Pillai, Kumar Appaiah, Rahul Vaze, Navin Kashyap:
Deadline Constrained Packet Scheduling in the Presence of an Energy Harvesting Jammer. IEEE Trans. Green Commun. Netw. 5(1): 278-290 (2021) - 2020
- Haseen Rahman, Ankith Vinayachandran, Sibi Raj B. Pillai, Kumar Appaiah, Rahul Vaze:
A Game Theoretic Model for Deadline Constrained Packet Scheduling with an Energy Harvesting Jammer. ICNC 2020: 216-221 - 2018
- Vinay Chamola, Bhaskar Krishnamachari, Biplab Sikdar:
Green Energy and Delay Aware Downlink Power Control and User Association for Off-Grid Solar-Powered Base Stations. IEEE Syst. J. 12(3): 2622-2633 (2018) - Priya Vinayak, Ajeet Singh, Sameer Sapra, Madhusudan Singh, Bhaskar Mitra:
A Solution Processed CdSe N Ano-Platelets Based Sensor for Cd Detection. IEEE SENSORS 2018: 1-4 - 2017
- Vinay Chamola, Biplab Sikdar, Bhaskar Krishnamachari:
Delay Aware Resource Management for Grid Energy Savings in Green Cellular Base Stations With Hybrid Power Supplies. IEEE Trans. Commun. 65(3): 1092-1104 (2017) - 2016
- Vinay Chamola, Bhaskar Krishnamachari, Biplab Sikdar:
An Energy and Delay Aware Downlink Power Control Strategy for Solar Powered Base Stations. IEEE Commun. Lett. 20(5): 954-957 (2016) - 2014
- Vinay S. Bhaskar, Abhishek Kumar Singh, Jyoti Dhruw, Anubha Parashar, Mradula Sharma:
Business and Social Behaviour Intelligence Analysis Using PSO. Int. J. Interact. Multim. Artif. Intell. 2(6): 69-74 (2014) - 2011
- Vijay Bhaskar Semwal, Vinay Bhaskar Semwal, Meenakshi Sati, Shirshu Verma:
Accurate location estimation of moving object In Wireless Sensor network. Int. J. Interact. Multim. Artif. Intell. 1(4): 71-75 (2011) - Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda:
500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". ISVLSI 2011: 72-77 - Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa:
Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. VLSI Design 2011: 130-134 - Vijay Bhaskar Semwal, K. Susheel Kumar, Vinay S. Bhaskar, Meenakshi Sati:
Accurate location estimation of moving object with energy constraint & adaptive update algorithms to save data. CoRR abs/1108.1321 (2011) - 2010
- Balaji Srinivasan, Vinay Bhaskar Chandratre:
An Improved High Resolution CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2010: 335-338 - 2008
- Balaji Srinivasan, Vinay Bhaskar Chandratre, Menka Tewani:
0.35µ, 1 GHz, CMOS Timing Generator Using Array of Digital Delay Lock Loops. VLSI Design 2008: 613-619
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