• case-insensitive prefix search: default
  e.g., sig matches "SIGIR" as well as "signal"
• exact word search: append dollar sign ($) to word
  e.g., graph$ matches "graph", but not "graphics"
• boolean and: separate words by space
  e.g., codd model
• boolean or: connect words by pipe symbol (|)
  e.g., graph|network

Update May 7, 2017: Please note that we had to disable the phrase search operator (.) and the boolean not operator (-) due to technical problems. For the time being, phrase search queries will yield regular prefix search result, and search terms preceded by a minus will be interpreted as regular (positive) search terms.

found 40 matches

• 2023
• 
  Kaushik Das, Sambhu Nath Pradhan:
  Hardware architecture design for complementary ensemble empirical mode decomposition algorithm. Integr. 91: 153-164 (2023)
• 
  Vivek Kumar Singh, Abhishek Nag, Abhishek Bhattacharjee, Sambhu Nath Pradhan:
  Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA. J. Circuits Syst. Comput. 32(7): 2350113:1-2350113:19 (2023)
• 2022
• 
  Abhishek Bhattacharjee, Abhishek Nag, Kaushik Das, Sambhu Nath Pradhan:
  Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation. J. Electron. Test. 38(1): 91-105 (2022)
• 
  Apangshu Das, Vivek Kumar Singh, Sambhu Nath Pradhan:
  Shared reduced ordered binary decision diagram-based thermal-aware network synthesis. Int. J. Circuit Theory Appl. 50(6): 2271-2286 (2022)
• 
  Vivek Kumar Singh, Abhishek Nag, Sambhu Nath Pradhan:
  Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks. Int. J. Embed. Syst. 15(4): 326-332 (2022)
• 2021
• 
  Abhishek Bhattacharjee, Dheeraj Kumar Sahu, Sambhu Nath Pradhan:
  Lookup table-based negative-bias temperature instability effect and leakage power co-optimization using genetic algorithm approach. Int. J. Circuit Theory Appl. 49(7): 1902-1915 (2021)
• 
  Kaushik Das, Sambhu Nath Pradhan:
  Field-programmable gate array-based design for real-time computation of ensemble empirical mode decomposition. Int. J. Circuit Theory Appl. 49(8): 2312-2328 (2021)
• 
  Abhishek Bhattacharjee, Sambhu Nath Pradhan:
  NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor. J. Circuits Syst. Comput. 30(11): 2120004:1-2120004:21 (2021)
• 
  Koel Datta Purkayastha, Ritesh Kishore Mishra, Arunava Shil, Sambhu Nath Pradhan:
  IoT Based Design of Air Quality Monitoring System Web Server for Android Platform. Wirel. Pers. Commun. 118(4): 2921-2940 (2021)
• 2020
• 
  Somnath Roy Choudhury, Sambhu Nath Pradhan:
  An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI. IEEE Access 8: 216365-216385 (2020)
• 
  Kaushik Das, Debanjali Nath, Sambhu Nath Pradhan:
  FPGA and ASIC realisation of EMD algorithm for real-time signal processing. IET Circuits Devices Syst. 14(6): 741-749 (2020)
• 
  Kaushik Das, Sambhu Nath Pradhan:
  An efficient hardware realization of EMD for real-time signal processing applications. Int. J. Circuit Theory Appl. 48(12): 2202-2218 (2020)
• 
  Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan:
  Low power transistor level synthesis of finite state machines using a novel dual gating technique. Int. J. Embed. Syst. 13(4): 431-438 (2020)
• 
  Apangshu Das, Sambhu Nath Pradhan:
  An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis. Int. J. Interact. Multim. Artif. Intell. 6(4): 26-38 (2020)
• 
  Apangshu Das, Yallapragada C. Hareesh, Sambhu Nath Pradhan:
  NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed-Muller Network Synthesis Using Parallel Tabular Technique. J. Circuits Syst. Comput. 29(15): 2020008:1-2020008:23 (2020)
• 2019
• 
  Somnath Roy Choudhury, Sambhu Nath Pradhan:
  DOTFloor-A Diffusion Oriented Time-Improved Floorplanner for Macrocells. IEEE Access 7: 172074-172087 (2019)
• 
  Priyanka Choudhury, Kanchan Manna, Vivek Rai, Sambhu Nath Pradhan:
  Thermal-Aware Partitioning and Encoding of Power-Gated FSM. J. Circuits Syst. Comput. 28(9): 1950144:1-1950144:14 (2019)
• 
  Abhishek Nag, Subhajit Das, Sambhu Nath Pradhan:
  Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. J. Circuits Syst. Comput. 28(5): 1920003:1-1920003:20 (2019)
• 2018
• 
  Ashim Saha, Sambhu Nath Pradhan:
  Facial expression recognition based on eigenspaces and principle component analysis. Int. J. Comput. Vis. Robotics 8(2): 190-200 (2018)
• 2017
• 
  Sambhu Nath Pradhan, Priyanka Choudhury, Debanjali Nath:
  Transistor level realisation of power gated FSM. Int. J. Comput. Aided Eng. Technol. 9(3): 351-371 (2017)
• 
  Abhishek Nag, Debanjali Nath, Sambhu Nath Pradhan:
  Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. J. Circuits Syst. Comput. 26(3): 1750041:1-1750041:12 (2017)
• 2016
• 
  Abhishek Nag, Sambhu Nath Pradhan:
  An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. J. Circuits Syst. Comput. 25(5): 1650033:1-1650033:21 (2016)
• 
  Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan:
  Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. J. Circuits Syst. Comput. 25(5): 1650044:1-1650044:26 (2016)
• 
  Apangshu Das, Sambhu Nath Pradhan:
  Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. VLSI Design 2016: 3191286:1-3191286:14 (2016)
• 2015
• 
  Sambhu Nath Pradhan, Angshuman Chakraborty, Abhishek Nag, Debanjali Nath:
  Layout-oriented look up table-based dual threshold approach to reduce leakage. Int. J. Comput. Aided Eng. Technol. 7(4): 456-480 (2015)
• 
  Apangshu Das, Sambhu Nath Pradhan:
  Thermal aware FPRM based AND-XOR network synthesis of logic circuits. ReTIS 2015: 497-502
• 
  Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan:
  Thermal aware AND-OR-XOR network synthesis. VDAT 2015: 1-6
• 2014
• 
  Debanjali Nath, Priyanka Choudhury, Abhishek Nag, Sambhu Nath Pradhan:
  Power gating architecture implementation inside clock period to reduce power. Int. J. Comput. Aided Eng. Technol. 6(3): 310-323 (2014)
• 2013
• 
  Angshuman Chakraborty, Sambhu Nath Pradhan:
  Gate level leakage minimisation at 90 nm technology. Int. J. Comput. Aided Eng. Technol. 5(4): 375-386 (2013)
• 
  Debanjali Nath, Priyanka Choudhury, Sambhu Nath Pradhan:
  Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). VDAT 2013: 160-168

skipping 10 more matches