- Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura:
A Packet Classifier Using a Parallel Branching Program Machine. DSD 2010: 745-752 - Malek Naoues, Laurent Alaus, Dominique Noguet:
A Common Operator for FFT and Viterbi Algorithms. DSD 2010: 309-313 - Son Truong Nguyen, Shigeru Oyanagi:
A Low Cost Single-Cycle Router Based on Virtual Output Queuing for On-chip Networks. DSD 2010: 60-67 - Vrishali Vijay Nimbalkar, Kuruvilla Varghese:
In-channel Flow Control Scheme for Network-on-Chip. DSD 2010: 459-466 - Juan Núñez
, Maria J. Avedillo
, José M. Quintana
:
Evaluation of RTD-CMOS Logic Gates. DSD 2010: 621-627 - Andrés Otero
, Angel Morales-Cas, Jorge Portilla
, Eduardo de la Torre, Teresa Riesgo:
A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD 2010: 88-95 - Maurizio Palesi, Rickard Holsmark, Xiaohang Wang, Shashi Kumar, Mei Yang, Yingtao Jiang, Vincenzo Catania:
An Efficient Technique for In-order Packet Delivery with Adaptive Routing Algorithms in Networks on Chip. DSD 2010: 37-44 - Muhammad Adeel Pasha, Steven Derrien, Olivier Sentieys
:
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes. DSD 2010: 493-500 - Ahmad Patooghy
, Hamed Tabkhi, Seyed Ghassem Miremadi:
An Efficient Method to Reliable Data Transmission in Network-on-Chips. DSD 2010: 467-474 - Fernando Pescador, Eduardo Juárez Martínez
, David Samper Martínez, César Sanz
, Mickaël Raulet:
A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder. DSD 2010: 123-129 - Stanislaw J. Piestrak:
On Reducing Error Rate of Data Protected Using Systematic Unordered Codes in Asymmetric Channels. DSD 2010: 133-140 - Zdenek Prikryl, Karel Masarík, Tomás Hruska, Adam Husár:
Generated Cycle-Accurate Profiler for C Language. DSD 2010: 263-268 - Adolfo Recio
, Peter M. Athanas:
Physical Layer for Spectrum-Aware Reconfigurable OFDM on an FPGA. DSD 2010: 321-327 - Frank Reichenbach, Alexander Wold:
Multi-core Technology -- Next Evolution Step in Safety Critical Systems for Industrial Applications? DSD 2010: 339-346 - José Luis Risco-Martín
, José Manuel Colmenar, David Atienza, José Ignacio Hidalgo
:
Simulation of High-Performance Memory Allocators. DSD 2010: 275-282 - Antoni Roca, José Flich
, Federico Silla, José Duato
:
A Latency-Efficient Router Architecture for CMP Systems. DSD 2010: 165-172 - Nicolas Roudel, François Berry, Jocelyn Sérot, Laurent Eck:
A New High-Level Methodology for Programming FPGA-Based Smart Camera. DSD 2010: 573-578 - Martin Rozkovec, Jiri Jenícek, Ondrej Novák:
Application Dependent FPGA Testing Method. DSD 2010: 525-530 - Jochem H. Rutgers, Pascal T. Wolkotte, Philip K. F. Hölzenspies, Jan Kuper, Gerard J. M. Smit:
An Approximate Maximum Common Subgraph Algorithm for Large Digital Circuits. DSD 2010: 699-705 - Richard Ruzicka:
Gracefully Degrading Circuit Controllers Based on Polytronics. DSD 2010: 809-812 - Sameer D. Sahasrabuddhe, Sreenivas Subramanian, Kunal P. Ghosh, Kavi Arya, Madhav P. Desai:
A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems. DSD 2010: 147-154 - Imtiaz Sajid, Sotirios G. Ziavras
, Muhammad Mansoor Ahmed
:
Hardware-Based Speed Up of Face Recognition Towards Real-Time Performance. DSD 2010: 763-770 - Mohammad Salehi, Amirali Baniasadi:
Storage-Aware Value Prediction. DSD 2010: 722-728 - Mostafa E. Salehi
, Hamed Dorosti
, Sied Mehdi Fakhraie:
Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications. DSD 2010: 269-272 - Nastaran Salehi, Ahmad Khadem Zadeh, Arash Dana:
Power Distribution in NoCs Through a Fuzzy Based Selection Strategy for Adaptive Routing. DSD 2010: 45-52 - Rubén Salvador
, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. DSD 2010: 96-103 - Tsutomu Sasao:
On the Numbers of Variables to Represent Multi-valued Incompletely Specified Functions. DSD 2010: 420-423 - Bibhash Sen
, Anik Sengupta
, Mamata Dalui, Biplab K. Sikdar
:
Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit. DSD 2010: 613-620 - Ricardo Severino
, Manish Batsa, Mário Alves
, Anis Koubaa
:
A Traffic Differentiation Add-On to the IEEE 802.15.4 Protocol: Implementation and Experimental Validation over a Real-Time Operating system. DSD 2010: 501-508 - Basher Shehan, Ralf Jahr, Sascha Uhrig, Theo Ungerer:
Reconfigurable Grid Alu Processor: Optimization and Design Space Exploration. DSD 2010: 71-79