- Hafizur Rahaman
, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. IET Comput. Digit. Tech. 4(5): 428-437 (2010) - Ryan N. Rakvic, José González, Qiong Cai, Pedro Chaparro, Grigorios Magklis, Antonio González
:
Energy efficiency via thread fusion and value reuse. IET Comput. Digit. Tech. 4(2): 114-125 (2010) - Debasri Saha, Susmita Sur-Kolay:
Robust intellectual property protection of VLSI physical design. IET Comput. Digit. Tech. 4(5): 388-399 (2010) - Harikrishna Samala, Aravind Dasu:
Methodology to derive resource aware context adaptable architectures for FPGAs. IET Comput. Digit. Tech. 4(1): 73-88 (2010) - X. She, N. Li:
Low-overhead single-event upset hardened latch using programmable resistance cells. IET Comput. Digit. Tech. 4(5): 420-427 (2010) - Matthew Shelburne, Cameron D. Patterson, Peter Athanas, Mark Jones, Brian S. Martin, Ryan Fong:
MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip. IET Comput. Digit. Tech. 4(3): 159-169 (2010) - Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech. 4(3): 196-210 (2010) - Arvind Sudarsanam, Robert Collier Barnes, J. Carver, Ramachandra Kallam, Aravind Dasu:
Dynamically reconfigurable systolic array accelerators: A case study with extended Kalman filter and discrete wavelet transform algorithms. IET Comput. Digit. Tech. 4(2): 126-142 (2010) - Bharat Sukhwani, Martin C. Herbordt:
FPGA acceleration of rigid-molecule docking codes. IET Comput. Digit. Tech. 4(3): 184-195 (2010) - Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin:
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction. IET Comput. Digit. Tech. 4(4): 317-324 (2010) - Shervin Vakili, Sied Mehdi Fakhraie, Siamak Mohammadi
:
Evolvable multi-processor: A novel MPSoC architecture with evolvable task decomposition and scheduling. IET Comput. Digit. Tech. 4(2): 143-156 (2010) - Kristofer Vorwerk, Andrew A. Kennings, Val Pevzner, Arun Kundu, Madhu Raman, Julien Dunoyer, Yaun-shung Hsu:
Power minimisation during field programmable gate array placement. IET Comput. Digit. Tech. 4(3): 170-183 (2010) - (Withdrawn) Scheme to minimise short effects of single-event upsets in triple-modular redundancy. IET Comput. Digit. Tech. 4(1): 50-55 (2010)