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Srinivas Devadas : Delay Test Generation for Synchronous Sequential Circuits. ITC 1989 : 144-152 share record
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Srinivas Devadas , Hi-Keung Tony Ma , A. Richard Newton : Redundancies and Don't Cares in Sequential Logic Synthesis. ITC 1989 : 491-500 share record
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Chryssa Dislis , I. D. Dear , J. R. Miles , S. C. Lau , Anthony P. Ambler : Cost Analysis of Test Method Environments. ITC 1989 : 875-883 share record
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Arthur E. Downey : "ATG" Test Generation Software. ITC 1989 : 829-837 share record
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Samuel H. Duncan : A BIST Design Methodology Experiment. ITC 1989 : 755-762 share record
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Rolf Ernst , S. Sutarwala , J.-Y. Jou : TSG: A Test System Generator for Debugging and Regression Test of High-Level Behavioral Synthesis Tools. ITC 1989 : 937 share record
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Michele Favalli , Piero Olivo , Maurizio Damiani , Bruno Riccò : CMOS Design for Improved IC Testability. ITC 1989 : 934 share record
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Manoj Franklin , Kewal K. Saluja , Kozo Kinoshita : Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. ITC 1989 : 327-336 share record
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David Grabel : Data Verification: A Prerequisite for Heuristic Diagnostics. ITC 1989 : 519-526 share record
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D. J. Hall , Anthony W. Sloman , G. S. Plows : Rapid Data Acquisition for E-Beam Testing. ITC 1989 : 928 share record
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Andy Halliday , Greg Young , Alfred L. Crouch : Prototype Testing Simplified by Scannable Buffers and Latches. ITC 1989 : 174-181 share record
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Peter Hansen : Testing Conventional Logic and Memory Clusters Using Boundary Scan Devices as Virtual ATE Channels. ITC 1989 : 166-173 share record
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Wallace Harwood , Mark McDermott : Testability Features of the MC68332 Modular Microcontroller. ITC 1989 : 615-623 share record
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Abu S. M. Hassan , Vinod K. Agarwal , Janusz Rajski , Benoit Nadeau-Dostie : Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC 1989 : 700-711 share record
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Kazumi Hatayama , Mitsuji Ikeda , Terumine Hayashi , Masahiro Takakura , Kuniaki Kishida , Shun Ishiyama : Enhanced Delay Test Generator for High-Speed Logic LSIs. ITC 1989 : 161-165 share record
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David Haupert , Fu-Gin Chen , David Lee : VLSI Package Reliability Risk Due to Accelerated Environmental Testing. ITC 1989 : 938 share record
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Sybille Hellebrand , Hans-Joachim Wunderlich : The Pseudo-Exhaustive Test of Sequential Circuits. ITC 1989 : 19-27 share record
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Eugene R. Hnatek , Billy R. Livesay : Quality Issues of High Pin Count Fine Pitch VLSI Packages. ITC 1989 : 397-422 share record
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Ching-Wen Hsue : Clock Signal Distribution Network for High-Speed Testers. ITC 1989 : 199-207 share record
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Raghu V. Hudli , Sharad C. Seth : Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. ITC 1989 : 364-372 share record
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Richard Illman , Stephen Clarke : Built-In Self-Test of the Macrolan Chip. ITC 1989 : 735-744 share record
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Marcel Jacomet : FANTESTIC: Towards a Powerful Fault Analysis and Test Pattern Generator for Integrated Circuits. ITC 1989 : 633-642 share record
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Najmi T. Jarwala , Chi W. Yau : A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects. ITC 1989 : 63-70 share record
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Najmi T. Jarwala , Chi W. Yau : A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects. ITC 1989 : 71-77 share record
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Bozena Kaminska , Yvon Savaria : Design-for-Testability Using Test Design Yield and Decision Theory. ITC 1989 : 884-892 share record
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Shuji Kikuchi , Yoshihiko Hayashi , Takashi Matsumoto , Ryozou Yoshino , Ryuichi Takagi : A 250 MHz Shared-Resource VLSI Test System with High Pin Count and Memory Test Capability. ITC 1989 : 558-566 share record
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Phillip N. King : Flexible, High-Performance Pin Electronics Implementation. ITC 1989 : 787-794 share record
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Kenrick Koo , Steve Ramseyer , Al Tejeda : A Testing Methodology for New-Generation Specialty Memory Devices. ITC 1989 : 452-460 share record
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Rainer Kraus , Oskar Kowarik , Kurt Hoffmann , Dieter Oberle : Design for Test of Mbit DRAMs. ITC 1989 : 316-321 share record
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John L. LaMay , Dan C. Caldwell : A Telecommunications Line Interface Test System Architecture. ITC 1989 : 216-221