- Franco Fummi, Giovanni Perbellini, Davide Quaglia, R. Trenti:
Exploration of Network Alternatives for Middleware-centric Embedded System Design. DSD 2010: 291-297 - Ye Gao, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A Load-Forwarding Mechanism for the Vector Architecture in Multimedia Applications. DSD 2010: 412-415 - Ismael Gómez, Massimo Camatel, Jordi Bracke, Vuk Marojevic, Antoni Gelonch, Fabrizio Vacca, Guido Masera:
ALOE-Based Flexible LDPC Decoder. DSD 2010: 314-320 - Kees Goossens, Dongrui She, Aleksandar Milutinovic, Anca Mariana Molnos:
Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications. DSD 2010: 107-114 - Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf:
Architectural Vulnerability Factor Estimation with Backwards Analysis. DSD 2010: 605-612 - Yi He, Ju Ren, Mei Wen, Qianming Yang, Nan Wu, Chunyuan Zhang:
Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. DSD 2010: 823-830 - Dan Hotoleanu, Octavian Cret, Alin Suciu, Tamas Györfi, Lucia Vacariu:
Real-Time Testing of True Random Number Generators Through Dynamic Reconfiguration. DSD 2010: 247-250 - Marcus Jeitler, Jakob Lechner:
Low Latency Recovery from Transient Faults for Pipelined Processor Architectures. DSD 2010: 219-225 - Subayal Khan, Kari Tiensyrjä, Jari Nurmi:
Instantiating GENESYS Application Architecture Modeling via UML 2.0 Constructs and MARTE Profile. DSD 2010: 251-254 - Paris Kitsos, Nicolas Sklavos, Athanassios N. Skodras:
Low Power FPGA Implementations of 256-bit Luffa Hash Function. DSD 2010: 416-419 - Somayyeh Koohi, Alireza Shafaei, Shaahin Hessabi:
Scalable Architecture for Wavelength-Switched Optical NoC with Multicasting Capability. DSD 2010: 398-403 - George Kornaros, Antonios Motakis:
On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms. DSD 2010: 355-362 - Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel:
The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption. DSD 2010: 644-651 - René Kothe, Heinrich Theodor Vierhaus:
Test Data and Power Reductions for Transition Delay Tests for Massive-Parallel Scan Structures. DSD 2010: 283-290 - Tim Kranich, Mladen Berekovic:
NoC Switch with Credit Based Guaranteed Service Support Qualified for GALS Systems. DSD 2010: 53-59 - Deepak Kumar, Pankaj Kumar, Manisha Pattanaik:
Performance Analysis of 90nm Look Up Table (LUT) for Low Power Application. DSD 2010: 404-407 - Tobias Lange, Naim Harb, Haisheng Liu, Smaïl Niar, Rabie Ben Atitallah:
An Improved Automotive Multiple Target Tracking System Design. DSD 2010: 255-258 - Felipe Lavratti, Alex R. Pinto, Letícia Maria Veiras Bolzani, Fabian Vargas, Carlos Barros Montez, Fernando Hernandez, Edmundo Gatti, C. Silva:
Evaluating a Transmission Power Self-Optimization Technique for WSN in EMI Environments. DSD 2010: 509-515 - Igor Lemberski, Petr Fiser:
Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. DSD 2010: 155-162 - Barend van Liempd, Daniel Herrera, Miguel E. Figueroa:
An FPGA-Based Accelerator for Analog VLSI Artificial Neural Network Emulation. DSD 2010: 771-778 - Sonia López, Oscar Garnica, David H. Albonesi, Steven G. Dropsho, Juan Lanchares, José Ignacio Hidalgo:
Adaptive Cache Memories for SMT Processors. DSD 2010: 331-338 - Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas:
Path-Delay Fault Testing in Embedded Content Addressable Memories. DSD 2010: 519-524 - Shohreh Sharif Mansouri, Elena Dubrova:
An Improved Hardware Implementation of the Grain Stream Cipher. DSD 2010: 433-440 - Andrea Marongiu, Paolo Burgio, Luca Benini:
Evaluating OpenMP Support Costs on MPSoCs. DSD 2010: 191-198 - Pedro Miguens Matutino, Ricardo Chaves, Leonel Sousa:
Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations. DSD 2010: 243-246 - Cor Meenderinck, Ben H. H. Juurlink:
A Case for Hardware Task Management Support for the StarSS Programming Model. DSD 2010: 347-354 - Dmitri Mironov, Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Structurally Synthesized Multiple Input BDDs for Speeding Up Logic-Level Simulation of Digital Circuits. DSD 2010: 658-663 - Craig Moore, Wim Meeus, Harald Devos, Dirk Stroobandt:
A Parallel for Loop Memory Template for a High Level Synthesis Compiler. DSD 2010: 449-455 - Félix Moreno, Ignacio López, Ricardo Sanz:
A Design Process for Hardware/Software System Co-design and its Application to Designing a Reconfigurable FPGA. DSD 2010: 556-562 - Saad Mubeen, Shashi Kumar:
Designing Efficient Source Routing for Mesh Topology Network on Chip Platforms. DSD 2010: 181-188