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2020 – today
- 2024
[c11]I-Lun Tseng
:
Challenges in Floorplanning and Macro Placement for Modern SoCs. ISPD 2024: 71-72- 2022
- [c10]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible chip placement via reinforcement learning: late breaking results. DAC 2022: 1392-1393 - [i6]Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen:
Flexible Multiple-Objective Reinforcement Learning for Chip Placement. CoRR abs/2204.06407 (2022)
2010 – 2019
- 2019
- [c9]I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Chun Ming Tommy Yip, Zhinan Chen, Jonathan Ong:
A System for Standard Cell Routability Checking and Placement Routability Improvements. APCCAS 2019: 125-128 - 2018
- [c8]I-Lun Tseng, Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong:
An Automated System for Checking Lithography Friendliness of Standard Cells. APCCAS 2018: 261-265 - [c7]Yongfu Li, I-Lun Tseng, Zhao Chuan Lee, Valerio Perez, Vikas Tripathi, Yoong Seang Jonathan Ong:
Identifying Lithography Weak-Points of Standard Cells with Partial Pattern Matching. ISVLSI 2018: 417-422 - [i5]Vikas Tripathi, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jason Khaw, Jonathan Ong:
In Design DFM Rule Scoring and Fixing Method using ICV. CoRR abs/1805.10016 (2018) - [i4]Yongfu Li, Valerio Perez, I-Lun Tseng, Zhao Chuan Lee, Vikas Tripathi, Jason Khaw, Yoong Seang Jonathan Ong:
Advanced In-Design Auto-Fixing Flow for Cell Abutment Pattern Matching Weakpoints. CoRR abs/1805.10283 (2018) - [i3]I-Lun Tseng, Valerio Perez, Yongfu Li, Zhao Chuan Lee, Vikas Tripathi, Yoong Seang Jonathan Ong:
Creation and Fixing of Lithography Hotspots with Synopsys Tools. CoRR abs/1808.05998 (2018) - [i2]Vikas Tripathi, Valerio Perez, Yongfu Li, Zhao Chuan Lee, I-Lun Tseng, Jonathan Ong:
Context-Aware DFM Rule Analysis and Scoring Using Machine Learning. CoRR abs/1808.05999 (2018) - [i1]I-Lun Tseng, Yongfu Li, Valerio Perez, Vikas Tripathi, Zhao Chuan Lee, Yoong Seang Jonathan Ong:
An Automated System for Checking Lithography Friendliness of Standard Cells. CoRR abs/1810.01446 (2018) - 2013
- [j2]Yao-Lin Chang, I-Lun Tseng:
A parallel dual-scanline algorithm for partitioning parameterized 45-degree polygons. ACM Trans. Design Autom. Electr. Syst. 18(4): 59:1-59:18 (2013) - [c6]Hsin-Hung Liu, Rung-Bin Lin, I-Lun Tseng:
Relocatable and resizable SRAM synthesis for via configurable structured ASIC. ISQED 2013: 494-501 - [c5]Yao-I Tseng, I-Lun Tseng, Adam Postula:
Boolean mask operations on parameterized 45-degree polygons. MWSCAS 2013: 453-456 - [c4]Yao-I Tseng, I-Lun Tseng, Tsao Hsiao Huang, Adam Postula:
Fast partitioning of parameterized 45-degree polygons into parameterized trapezoids. NEWCAS 2013: 1-4 - 2010
- [c3]I-Lun Tseng, Huan-Wen Chen, Che-I Lee, Adam Postula:
Constraint-Based Dogleg Channel Routing with Via Minimization. IC-AI 2010: 666-672
2000 – 2009
- 2008
- [b1]I-Lun Tseng:
Estimation of Analog Layout Parasitics with Parameterized Polygons. University of Queensland, Australia, 2008 - [j1]I-Lun Tseng, Adam Postula:
Partitioning parameterized 45-degree polygons with constraint programming. ACM Trans. Design Autom. Electr. Syst. 13(3): 52:1-52:29 (2008) - 2006
- [c2]I-Lun Tseng, Adam Postula:
An efficient algorithm for partitioning parameterized polygons into rectangles. ACM Great Lakes Symposium on VLSI 2006: 366-371 - 2004
- [c1]I-Lun Tseng, Adam Postula:
GBLD: A Formal Model for Layout Description and Generation. FDL 2004: 661-672
Coauthor Index
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