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"Clock recovery circuit with adiabatic technology (quasi-static CMOS logic)."

W. K. Yeung et al. (2003)

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DOI: 10.1109/ISCAS.2003.1205928

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-04

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  dblp key:
  - conf/iscas/YeungCCP03
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  - https://dblp.org/rec/conf/iscas/YeungCCP03
W. K. Yeung, Cheong-Fat Chan, Chiu-sing Choy, Kong-Pang Pun:
Clock recovery circuit with adiabatic technology (quasi-static CMOS logic). ISCAS (2) 2003: 185-187

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