"3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat)."

Kazuo Tsutsui et al. (2017)

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DOI: 10.1109/ASICON.2017.8252681

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-12

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Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai:
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON 2017: 1137-1140

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