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Takuya Saraya
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2020 – today
- 2024
- [c12]Masaharu Kobayashi, Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka:
Performance and Reliability of Nanosheet Oxide Semiconductor FETs with ALD-Grown InGaO for 3D Integration (Invited). IRPS 2024: 9 - 2023
- [c11]Kaito Hikake, Zhuo Li, Junxiang Hao, Chitra Pandy, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi:
A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c10]Masahide Goto, Yuki Honda, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi
, Hiroshi Toshiyoshi, Toshiro Hiramoto:
3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers. Imaging Sensors and Systems 2022: 1-4 - 2021
- [c9]Toshiro Hiramoto, Takuya Saraya:
Recent Progress of Double/Dual-Gate Silicon IGBT Technologies. ASICON 2021: 1-4
2010 – 2019
- 2019
- [c8]Masahide Goto
, Joeri De Vos, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Eiji Higurashi
, Yuki Honda, Takuya Saraya, Masaharu Kobayashi, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers. 3DIC 2019: 1-4 - [c7]Fei Mo
, Yusaku Tagawa, Takuya Saraya, Toshiro Hiramoto, Masaharu Kobayashi:
Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method. NVMTS 2019: 1-5 - 2018
- [c6]Takuya Hoshii, Kazuyoshi Furukawa, Kuniyuki Kakushima, Masahiro Watanabe, Naoyuki Shigvo, Takuya Saraya, Toshihiko Takakura, Kazuo Itou, Munetoshi Fukui, Shinichi Suzuki, Kiyoshi Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Lwai:
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately. ESSDERC 2018: 26-29 - [c5]Masahide Goto
, Yuki Honda, Toshihisa Watabe, Kei Hagiwara, Masakazu Nanba, Yoshinori Iguchi, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi
, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration. ISCAS 2018: 1-4 - [c4]Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura
, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai:
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. VLSI Circuits 2018: 105-106 - 2017
- [c3]Kazuo Tsutsui, Kuniyuki Kakushima, Takuya Hoshii
, A. Nakajima, Shinichi Nishizawa, Hitoshi Wakabayashi, Iriya Muneta, K. Sato, Tomoko Matsudai, Wataru Saito, Takuya Saraya, K. Itou, M. Fukui, S. Suzuki, Masaharu Kobayashi, T. Takakura, Toshiro Hiramoto, Atsushi Ogura
, Y. Numasawa, Ichiro Omura, Hiromichi Ohashi, Hiroshi Iwai:
3D scaling for insulated gate bipolar transistors (IGBTs) with low Vce(sat). ASICON 2017: 1137-1140 - 2015
- [c2]Masahide Goto
, Kei Hagiwara, Yoshinori Iguchi, Hiroshi Ohtake, Takuya Saraya, Masaharu Kobayashi, Eiji Higurashi
, Hiroshi Toshiyoshi, Toshiro Hiramoto:
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers. 3DIC 2015: TS9.2.1-TS9.2.4 - 2013
- [j2]Nurul Ezaila Alias, Anil Kumar, Takuya Saraya, Shinji Miyano, Toshiro Hiramoto:
NBTI Reliability of PFETs under Post-Fabrication Self-Improvement Scheme for SRAM. IEICE Trans. Electron. 96-C(5): 620-623 (2013) - [j1]Toshiro Hiramoto, Anil Kumar, Takuya Saraya, Shinji Miyano:
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress. IEICE Trans. Electron. 96-C(6): 759-765 (2013) - 2011
- [c1]Toshiro Hiramoto, Anil Kumar, Tomoko Mizutani, Jun Nishimura, Takuya Saraya:
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs. CICC 2011: 1-4
Coauthor Index
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last updated on 2024-07-15 01:01 CEST by the dblp team
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