"Interface engineering of Si1-xGex gate stacks for high performance dual ..."

ChoongHyun Lee et al. (2017)

> Home

Details and statistics

DOI: 10.1109/ASICON.2017.8252540

access: closed

type: Conference or Workshop Paper

metadata version: 2023-09-30

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/asicon/LeeSMJBPKANHJ17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/asicon/LeeSMJBPKANHJ17
ChoongHyun Lee, Richard G. Southwick, Shogo Mochizuki, Paul Jamison, Ruqiang Bao, Rajan Pandey, Aniruddha Konar, Takashi Ando, Vijay Narayanan, Bala Haran, Hemanth Jagannathan:
Interface engineering of Si1-xGex gate stacks for high performance dual channel CMOS. ASICON 2017: 573-576

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.