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Syed Suhaib

Syed M. Suhaib

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affiliation: NVIDIA
affiliation (former): Virginia Tech, Blacksburg, Virginia, USA

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2020 – today

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2025
[c11]
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Minwoo Kang, Mingjie Liu, Ghaith Bany Hamad, Syed M. Suhaib, Haoxing Ren:
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware. DATE 2025: 1-6
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Yunsheng Bai, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren:
AssertionForge: Enhancing Formal Verification Assertion Generation with Structured Representation of Specifications and RTL. CoRR abs/2503.19174 (2025)
2024
[c10]
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Mingjie Liu, Minwoo Kang, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren:
Domain-Adapted LLMs for VLSI Design and Verification: A Case Study on Formal Verification. VTS 2024: 1-4
[i1]
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Minwoo Kang, Mingjie Liu, Ghaith Bany Hamad, Syed Suhaib, Haoxing Ren:
FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware. CoRR abs/2410.23299 (2024)

2000 – 2009

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2008
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
A Trace-Based Framework for Verifiable GALS Composition of IPs. IEEE Trans. Very Large Scale Integr. Syst. 16(9): 1176-1186 (2008)
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Syed Suhaib, Bijoy Antony Jose, Sandeep K. Shukla, Deepak Mathaikutty:
Formal Transformation of a KPN Specification to a GALS Implementation. FDL 2008: 84-89
2007
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Syed Suhaib:
Formal Methods for Intellectual Property Composition Across Synchronization Domains. Virginia Tech, Blacksburg, VA, USA, 2007
[c8]
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
Dataflow Architectures for GALS. FMGALS@MEMOCODE 2007: 33-50
2006
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Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla:
Validating Families of Latency Insensitive Protocols. IEEE Trans. Computers 55(11): 1391-1401 (2006)
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, Jean-Pierre Talpin:
Polychronous Methodology For System Design: A True Concurrency Approach. HLDVT 2006: 211-214
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
A Trace Based Framework for Validation of SoC Designs with GALS Systems. SoCC 2006: 247-250
2005
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
XFM: An incremental methodology for developing formal models. ACM Trans. Design Autom. Electr. Syst. 10(4): 589-609 (2005)
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
Validating families of latency insensitive protocols. HLDVT 2005: 127-134
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
System Level Design Methodology for System On Chips using Multi-Threaded Graphs. SoCC 2005: 133-136
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner, Jean-Pierre Talpin:
A Functional Programming Framework for Latency Insensitive Protocol Validation. FMGALS@MEMOCODE 2005: 169-188
2004
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Peng Li, Binoy Ravindran, Syed Suhaib, Shahrooz Feizabadi:
A Formally Verified Application-Level Framework for Real-Time Scheduling on POSIX Real-Time Operating Systems. IEEE Trans. Software Eng. 30(9): 613-629 (2004)
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla:
Effects of property ordering in an incremental formal modeling methodology. HLDVT 2004: 89-94
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Syed Suhaib, Deepak Mathaikutty, Sandeep K. Shukla, David Berner:
Extreme Formal Modeling (XFM) for Hardware Models. MTV 2004: 30-35

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