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2010 – 2019
- 2019
[c58]Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt:
Volcan: System Integration of HLS and HMC on FPGAs. ReConFig 2019: 1-2- 2018
- [c57]Abhi D. Rajagopala, Ron Sass, Andrew G. Schmidt, Matthew French:
Bridging the Gap between Advanced Memory and Heterogeneous Architectures. FCCM 2018: 226 - 2016
- [e2]Peter M. Athanas, René Cumplido, Claudia Feregrino, Ron Sass:
International Conference on ReConFigurable Computing and FPGAs, ReConFig 2016, Cancun, Mexico, November 30 - Dec. 2, 2016. IEEE 2016, ISBN 978-1-5090-3707-0 [contents] - 2014
- [j13]Yamuna Rajasekhar, Ron Sass:
Architecture and applications for an All-FPGA parallel computer. Clust. Comput. 17(2): 315-325 (2014) - [j12]Shweta Jain-Mendon, Ron Sass:
A hardware-software co-design approach for implementing sparse matrix vector multiplication on FPGAs. Microprocess. Microsystems 38(8): 873-888 (2014) - [c56]Bin Huang, Ron Sass, Nathan DeBardeleben, Sean Blanchard:
Harnessing Unreliable Cores in Heterogeneous Architecture: The PyDac Programming Model and Runtime. DSN 2014: 744-749 - [c55]Jürgen Becker, Ramachandran Vaidyanathan, Marco D. Santambrogio
, Jim Tørresen, Ron Sass, Philip Heng Wai Leong:
RAW Introduction and Committees. IPDPS Workshops 2014: 109-110 - 2013
- [c54]Yamuna Rajasekhar, Ron Sass:
A Novel Memory Subsystem and Computational Model for Parallel Reconfigurable Architectures. Euro-Par Workshops 2013: 444-453 - [c53]Bin Huang, Ron Sass, Nathan DeBardeleben, Sean Blanchard:
PyDac: A Resilient Run-Time Framework for Divide-and-Conquer Applications on a Heterogeneous Many-Core Architecture. Euro-Par Workshops 2013: 845-854 - [c52]Scott Buscemi, William V. Kritikos, Ron Sass:
A Range and Scaling Study of an FPGA-Based Digital Wireless Channel Emulator. FCCM 2013: 137-144 - [c51]Shanyuan Gao, Bin Huang, Ron Sass:
The Impact of Hardware Communication on a Heterogeneous Computing System. FCCM 2013: 234 - [c50]Shweta Jain-Mendon, Ron Sass:
Performance evaluation of Sparse Matrix-Matrix Multiplication. FPL 2013: 1-4 - 2012
- [j11]Andrew G. Schmidt, Neil Steiner, Matthew French, Ron Sass:
HwPMI: An Extensible Performance Monitoring Infrastructure for Improving Hardware Design and Productivity on FPGAs. Int. J. Reconfigurable Comput. 2012: 162404:1-162404:12 (2012) - [j10]Claudia Feregrino, Miguel Arias, Kris Gaj, Viktor K. Prasanna, Marco D. Santambrogio, Ron Sass:
Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10). Int. J. Reconfigurable Comput. 2012: 319827:1-319827:2 (2012) - [j9]Andrew G. Schmidt, William V. Kritikos, Shanyuan Gao, Ron Sass:
An Evaluation of an Integrated On-Chip/Off-Chip Network for High-Performance Reconfigurable Computing. Int. J. Reconfigurable Comput. 2012: 564704:1-564704:15 (2012) - [j8]William V. Kritikos, Andrew G. Schmidt, Ron Sass, Erik K. Anderson, Matthew French:
Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip. Int. J. Reconfigurable Comput. 2012: 872610:1-872610:11 (2012) - [j7]Andrew G. Schmidt, Siddhartha Datta, Ashwin A. Mendon, Ron Sass:
Investigation into scaling I/O bound streaming applications productively with an all-FPGA cluster. Parallel Comput. 38(8): 344-364 (2012) - [c49]Ashwin A. Mendon, Ron Sass, Zachary K. Baker, Justin L. Tripp:
Design and implementation of a hardware checkpoint/restart core. DSN Workshops 2012: 1-6 - [c48]Yamuna Rajasekhar, Rahul R. Sharma, Ron Sass:
An Extensible and Portable Tool Suite for Managing Multi-Node FPGA Systems. FCCM 2012: 117-120 - [c47]Ashwin A. Mendon, Bin Huang, Ron Sass:
A high performance, open source SATA2 core. FPL 2012: 421-428 - [c46]Scott Buscemi, Ron Sass:
Design and utilization of an FPGA cluster to implement a Digital Wireless Channel Emulator. FPL 2012: 635-638 - [c45]Yamuna Rajasekhar, Ron Sass:
Architecture and Applications for an All-FPGA Parallel Computer. ICPP Workshops 2012: 157-164 - [c44]Shweta Jain-Mendon, Ron Sass:
A case study of streaming storage format for sparse matrices. ReConFig 2012: 1-6 - [c43]Rahul R. Sharma, Yamuna Rajasekhar, Ron Sass:
Exploring hardware work queue support for lightweight threads in MPSoCs. ReConFig 2012: 1-6 - 2011
- [c42]Andrew G. Schmidt, Bin Huang, Ron Sass, Matthew French:
Checkpoint/Restart and Beyond: Resilient High Performance Computing with FPGAs. FCCM 2011: 162-169 - [c41]William V. Kritikos, Yamuna Rajasekhar, Andrew G. Schmidt, Ron Sass:
A Radix Tree Router for Scalable FPGA Networks. FPL 2011: 76-81 - [c40]Scott Buscemi, Ron Sass:
Design of a scalable digital Wireless Channel Emulator for networking radios. MILCOM 2011: 1858-1863 - [c39]Ron Sass, Andrew G. Schmidt, Scott Buscemi:
Reconfigurable Computing Cluster - A Five-Year Perspective of the Project. PARCO 2011: 595-602 - [c38]Andrew G. Schmidt, Ron Sass:
Improving FPGA Design and Evaluation Productivity with a Hardware Performance Monitoring Infrastructure. ReConFig 2011: 422-427 - 2010
- [c37]Shanyuan Gao, Andrew G. Schmidt, Ron Sass:
Impact of reconfigurable hardware on accelerating MPI_Reduce. FPT 2010: 29-36 - [c36]Robin Pottathuparambil, Ron Sass:
FPGA-based three-body molecular dynamics simulator. HPCS 2010: 599-605 - [c35]Andrew G. Schmidt, William V. Kritikos, Ron Sass, Erik K. Anderson, Matthew French:
Merging Programming Models and On-chip Networks to Meet the Programmable and Performance Needs of Multi-core Systems on a Programmable Chip. ReConFig 2010: 334-339 - [c34]Bin Huang, Andrew G. Schmidt, Ashwin A. Mendon, Ron Sass:
Investigating resilient high performance reconfigurable computing with minimally-invasive system monitoring. HPRCTA@SC 2010: 1-8 - [e1]Ron Sass, Russell Tessier:
18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010. IEEE Computer Society 2010, ISBN 978-0-7695-4056-6 [contents]
2000 – 2009
- 2009
- [j6]Ashwin A. Mendon, Andrew G. Schmidt, Ron Sass:
A Hardware Filesystem Implementation with Multidisk Support. Int. J. Reconfigurable Comput. 2009: 572860:1-572860:13 (2009) - [j5]Nathan DeBardeleben, Ron Sass, Daniel C. Stanzione Jr., Walter B. Ligon III:
Building problem-solving environments with the Arches framework. J. Syst. Softw. 82(7): 1137-1151 (2009) - [c33]Siddhartha Datta, Parag Beeraka, Ron Sass:
RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function. FCCM 2009: 88-95 - [c32]Andrew G. Schmidt, William V. Kritikos, Rahul R. Sharma, Ron Sass:
AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks. FCCM 2009: 271-274 - [c31]Robin Pottathuparambil, Ron Sass:
A parallel/vectorized double-precision exponential core to accelerate computational science applications. FPGA 2009: 285 - [c30]Shanyuan Gao, Andrew G. Schmidt, Ron Sass:
Hardware implementation of MPI_Barrier on an FPGA cluster. FPL 2009: 12-17 - [c29]Siddhartha Datta, Ron Sass:
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions. ReConFig 2009: 131-136 - 2008
- [j4]David Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
Achieving Programming Model Abstractions for Reconfigurable Computing. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 34-44 (2008) - [c28]Yamuna Rajasekhar, Yashodhan Phatak, Andrew G. Schmidt, William V. Kritikos, Ron Sass:
FPGA Session Control (FSC): Providing Remote Access to a Cluster of FPGAs. FCCM 2008: 298-299 - [c27]Andrew G. Schmidt, William V. Kritikos, Siddhartha Datta, Ron Sass:
Reconfigurable Computing Cluster Project: Phase I Brief. FCCM 2008: 300-301 - [c26]Yamuna Rajasekhar, William V. Kritikos, Andrew G. Schmidt, Ron Sass:
Teaching FPGA system design via a remote laboratory facility. FPL 2008: 687-690 - [c25]Ashwin A. Mendon, Ron Sass:
A Hardware Filesystem Implementation for High-Speed Secondary Storage. ReConFig 2008: 283-288 - 2007
- [c24]Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka:
Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing. FCCM 2007: 127-140 - [c23]Andrew G. Schmidt, Ron Sass:
Quantifying Effective Memory Bandwidth of Platform FPGAs. FCCM 2007: 337-338 - [c22]Kushal Datta, Ron Sass:
RBoot: Software Infrastructure for a Remote FPGA Laboratory. FCCM 2007: 343-344 - [c21]Andrew G. Schmidt, Ron Sass:
Characterizing Effective Memory Bandwidth of Designs with Concurrent High-Performance Computing Cores. FPL 2007: 601-604 - 2006
- [j3]Ron Sass, Brian Greskamp, Brian Leonard, Jeff Young, Srinivas Beeravolu:
Online architectures: A theoretical formulation and experimental prototype. Microprocess. Microsystems 30(6): 319-333 (2006) - [c20]David L. Andrews, Ron Sass, Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp:
The Case for High Level Programming Models for Reconfigurable Computers. ERSA 2006: 21-32 - [c19]Erik K. Anderson, Jason Agron, Wesley Peck, Jim Stevens, Fabrice Baijot, Ed Komp, Ron Sass, David Andrews:
Enabling a Uniform Programming Model Across the Software/Hardware Boundary. FCCM 2006: 89-98 - [c18]Jason Agron, Wesley Peck, Erik K. Anderson, David Andrews, Ed Komp, Ron Sass, Fabrice Baijot, Jim Stevens:
Run-Time Services for Hybrid CPU/FPGA Systems on Chip. RTSS 2006: 3-12 - 2005
- [c17]Brian Greskamp, Ron Sass:
A Virtual Machine for Merit-Based Runtime Reconfiguration. FCCM 2005: 287-288 - [c16]Krishna Muriki, Keith D. Underwood, Ron Sass:
RC-BLAST: Towards a Portable, Cost-Effective Open Source Hardware Implementation. IPDPS 2005 - [c15]Pradeep Nalabalapu, Ron Sass:
Bandwidth Management with a Reconfigurable Data Cache. IPDPS 2005 - 2004
- [j2]Keith D. Underwood, Walter B. Ligon III, Ron R. Sass:
An Analysis of the Cost Effectiveness of an Adaptable Computing Cluster. Clust. Comput. 7(4): 357-371 (2004) - [c14]Jeff Young, Ron Sass:
FERP Interface and Interconnect Cores for Stream Processing Applications. EUC 2004: 291-300 - [c13]Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass:
Automatic discovery, selection, and specialization of modules in RCADE. FPGA 2004: 256 - [c12]Brian Leonard, Jeff Young, Ron Sass:
Online placement infrastructure to support run-time reconfiguration. FPGA 2004: 256 - [c11]Nathan DeBardeleben, Walter B. Ligon III, Ron Sass:
Arches: An Infrastructure for PSE Development. HIPS 2004: 120-128 - 2003
- [j1]Keith D. Underwood, Walter B. Ligon III, Ron Sass:
Analysis of a prototype intelligent network interface. Concurr. Comput. Pract. Exp. 15(7-8): 751-777 (2003) - [c10]Ranjesh G. Jaganathan, Keith D. Underwood, Ron R. Sass:
A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC. FCCM 2003: 286-287 - [c9]Shyamnath Harinath, Ron Sass:
Reconfigurable Mapping Functions for Online Architectures. IPDPS 2003: 173 - [c8]Ranjesh G. Jaganathan, Keith D. Underwood, Ron Sass:
A Configurable Network Protocol for Cluster Based Communications using Modular Hardware Primitives on an Intelligent NIC. SC 2003: 22 - 2001
- [c7]Keith D. Underwood, Ron Sass, Walter B. Ligon III:
A Reconfigurable Extension to the Network Interface of Beowulf Clusters. CLUSTER 2001: 212- - [c6]Keith D. Underwood, Ron R. Sass, Walter B. Ligon III:
Acceleration of a 2D-FFT on an Adaptable Computing Cluster. FCCM 2001: 180-189 - [c5]Keith D. Underwood, Ron R. Sass, Walter B. Ligon III:
Cost effectiveness of an adaptable computing cluster. SC 2001: 54
1990 – 1999
- 1995
- [c4]Marwan Krunz, Ron Sass, Herman D. Hughes:
Statistical Characteristics and Multiplexing of MPEG Streams. INFOCOM 1995: 455-462 - 1994
- [c3]Ron Sass, Matt W. Mutka:
Transformations on Doubly Nested Loops. IFIP PACT 1994: 343-346 - [c2]Ron Sass, Matt W. Mutka:
Enabling unimodular transformations. SC 1994: 753-762 - 1993
- [c1]Chi-Ming Chiang, Qiang Du, Matt W. Mutka, Ron Sass:
An Empirical Study of Scalable Domain Decomposition Methods for a 2-D Parabolic Equation Solver. PPSC 1993: 687-690
Coauthor Index
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