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ORCIDMary Jane Irwin
- > Home > Persons > Mary Jane Irwin
Publications
- 2008
[j79]Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Design Space Exploration for 3-D Cache. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 444-455 (2008)- 2007
- [i1]Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin:
Leakage-Aware Interconnect for On-Chip Network. CoRR abs/0710.4731 (2007) - 2006
- [j70]Wei Zhang
, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embed. Comput. Syst. 5(1): 1-28 (2006) - 2005
- [c195]Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Leakage-Aware Interconnect for On-Chip Network. DATE 2005: 230-231 - [c190]Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin:
Three-Dimensional Cache Design Exploration Using 3DCacti. ICCD 2005: 519-524 - [c180]Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin:
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. VLSI Design 2005: 374-379 - 2004
- [j53]Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Characterization and modeling of run-time techniques for leakage power reduction. IEEE Trans. Very Large Scale Integr. Syst. 12(11): 1221-1233 (2004) - [c172]Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan:
Reducing leakage energy in FPGAs using region-constrained placement. FPGA 2004: 51-58 - [c153]Yuh-Fang Tsai, Ananth Hegde Ankadi, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides:
ChipPower: an architecture-level leakage simulator. SoCC 2004: 395-398 - 2003
- [j49]Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam:
Managing Leakage Energy in Cache Hierarchies. J. Instr. Level Parallelism 5 (2003) - [c144]Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Implications of technology scaling on leakage reduction techniques. DAC 2003: 187-190 - 2002
- [c125]Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam:
Leakage Energy Management in Cache Hierarchies. IEEE PACT 2002: 131-140 - [c108]David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin:
Evaluating Run-Time Techniques for Leakage Power Reduction. ASP-DAC/VLSI Design 2002: 31-38 - 2001
- [c97]Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai:
Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO 2001: 102-113
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