"A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM ..."

Hyun-Woo Lee et al. (2010)

Details and statistics

DOI: 10.1109/ISCAS.2010.5537703

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

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