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Jeng-Jie Peng

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2000 – 2009

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2003
[c6]
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Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang:
Active Device under Bond Pad to Save I/O Layout for High-pin-count SOC. ISQED 2003: 241-246
[c5]
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Ming-Dou Ker, Hsin-Chyh Hsu, Jeng-Jie Peng:
Electrostatic Discharge Implantation to Improve Machine-Model ESD Robustness of Stacked NMOS in Mixed-Voltage I/O Interface Circuits. ISQED 2003: 363-368
2002
[c4]
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Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang:
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits. ISCAS (5) 2002: 537-540
2001
[c3]
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Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh:
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. ICECS 2001: 113-116
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Ming-Dou Ker, Jeng-Jie Peng, Hsin-Chin Jiang:
ESD test methods on integrated circuits: an overview. ICECS 2001: 1011-1014

1990 – 1999

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1998
[c1]
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Ming-Dou Ker, Jeng-Jie Peng:
Layout design and verification for cell library to improve ESD/latchup reliability in deep-submicron CMOS technology. CICC 1998: 537-540

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