Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Automatic methodology for placing the guard rings into chip layout to ..."

Ming-Dou Ker et al. (2001)

> Home

Details and statistics

DOI: 10.1109/ICECS.2001.957690

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-18

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icecsys/KerJPS01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icecsys/KerJPS01
Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh:
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. ICECS 2001: 113-116

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.