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Journal Articles
- 2017
[j4]Gwo Giun Chris Lee, Chun-Hsi Huang, Chun-Fu (Richard) Chen
, Tai-Ping Wang:
Complexity-Aware Gabor Filter Bank Architecture Using Principal Component Analysis. J. Signal Process. Syst. 89(3): 431-444 (2017)- 2016
- [j3]Tong-Yu Hsieh, Tai-Ping Wang, Shuo Yang, Chin-An Hsu, Yi-Lung Lin:
An Area-Efficient Scalable Test Module to Support Low Pin-Count Testing. IEICE Trans. Electron. 99-C(3): 404-414 (2016) - 2009
- [j2]Ming-Der Shieh, Tai-Ping Wang, Der-Wei Yang:
Low-power register-exchange survivor memory architectures for Viterbi decoders. IET Circuits Devices Syst. 3(2): 83-90 (2009) - 2008
- [j1]Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu:
Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. IEICE Trans. Inf. Syst. 91-D(9): 2300-2311 (2008)
Conference and Workshop Papers
- 2019
- [c4]Shih-Yu Chen, Gwo Giun Chris Lee, Tai-Ping Wang, Chin-Wei Huang, Jia-Hong Chen, Chang-Ling Tsai:
Reconfigurable Edge via Analytics Architecture. AICAS 2019: 117-121 - 2016
- [c3]Gwo Giun Chris Lee, Shi-Yu Hung, Tai-Ping Wang, Chun-Fu (Richard) Chen, Chi-Kuang Sun, Yi-Hua Liao:
Efficient nuclei segmentation based on spectral graph partitioning. ISCAS 2016: 2723-2726 - 2007
- [c2]Jiun-Da Chen, Tai-Ping Wang, Chao-Lin Liu:
以文件分類技術預測股價趨勢 (Predicting Trends of Stock Prices with Text Classification Techniques) [In Chinese]. ROCLING 2007 - 2006
- [c1]Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang:
Efficient path metric access for reducing interconnect overhead in Viterbi decoders. ISCAS 2006
Coauthor Index
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