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2020 – today
- 2024
[j4]Mingyu Liang
, Yu Gan, Yueying Li, Carlos Torres, Abhishek Dhanotia, Mahesh Ketkar, Christina Delimitrou:
End-to-End Cloud Application Cloning With Ditto. IEEE Micro 44(4): 34-43 (2024)- [c14]Erick Carvajal Barboza, Mahesh Ketkar, Paul Gratz, Jiang Hu:
Aiding Microprocessor Performance Validation with Machine Learning. ISPASS 2024: 1-9 - 2023
- [c13]Mingyu Liang, Yu Gan, Yueying Li, Carlos Torres, Abhishek Dhanotia, Mahesh Ketkar, Christina Delimitrou:
Ditto: End-to-End Application Cloning for Networked Cloud Services. ASPLOS (2) 2023: 222-236 - [c12]Shruti Yadav Narayana, Jie Tong, Anish Krishnakumar, Nuriye Yildirim, Emily Shriver, Mahesh Ketkar, Ümit Y. Ogras:
MQL: ML-Assisted Queuing Latency Analysis for Data Center Networks. ISPASS 2023: 50-60 - [i6]Erick Carvajal Barboza, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Machine Learning for Microprocessor Performance Bug Localization. CoRR abs/2303.15280 (2023) - 2022
- [j3]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Patterns From Concurrent Execution Traces. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2758-2762 (2022) - [i5]Mingyu Liang, Yu Gan, Yueying Li, Carlos Torres, Abhishek Dhanotia, Mahesh Ketkar, Christina Delimitrou:
End-to-End Application Cloning for Distributed Cloud Microservices with Ditto. CoRR abs/2212.13867 (2022) - 2021
- [c11]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Automatic Microprocessor Performance Bug Detection. HPCA 2021: 545-556 - [c10]Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System Designs. ICCD 2021: 492-499 - [c9]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Message Flows from System-on-Chip Execution Traces. ISQED 2021: 374-380 - [c8]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
A Comparative Study of Specification Mining Methods for SoC Communication Traces. ISVLSI 2021: 31-36 - [i4]Hao Zheng, Md Rubel Ahmed, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Model Synthesis for Communication Traces of System-on-Chip Designs. CoRR abs/2102.06989 (2021) - 2020
- [c7]Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng:
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. ISQED 2020: 389-394 - [i3]Yuting Cao, Parijat Mukherjee, Mahesh Ketkar, Jin Yang, Hao Zheng:
Mining Message Flows using Recurrent Neural Networks for System-on-Chip Designs. CoRR abs/2005.01574 (2020) - [i2]Md Rubel Ahmed, Hao Zheng, Parijat Mukherjee, Mahesh C. Ketkar, Jin Yang:
Mining Message Flows from System-on-Chip Execution Traces. CoRR abs/2005.11221 (2020) - [i1]Erick Carvajal Barboza, Sara Jacob, Mahesh Ketkar, Michael Kishinevsky, Paul Gratz, Jiang Hu:
Automatic Microprocessor Performance Bug Detection. CoRR abs/2011.08781 (2020)
2010 – 2019
- 2019
- [c6]David Ke Hong, Ashkan Nikravesh, Z. Morley Mao, Mahesh Ketkar, Michael Kishinevsky:
PerfProbe: a systematic, cross-layer performance diagnosis framework for mobile platforms. MOBILESoft@ICSE 2019: 50-61
2000 – 2009
- 2009
- [j2]Shiyan Hu, Mahesh Ketkar, Jiang Hu:
Gate Sizing for Cell-Library-Based Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(6): 818-825 (2009) - [c5]Mahesh Ketkar, Eli Chiprout:
A microarchitecture-based framework for pre- and post-silicon power delivery analysis. MICRO 2009: 179-188 - 2007
- [c4]Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 - [c3]Shiyan Hu, Mahesh Ketkar, Jiang Hu:
Gate Sizing For Cell Library-Based Designs. DAC 2007: 847-852 - 2002
- [c2]Mahesh Ketkar, Sachin S. Sapatnekar:
Standby power optimization via transistor sizing and dual threshold voltage assignment. ICCAD 2002: 375-378 - 2000
- [j1]Kishore Kasamsetty, Mahesh Ketkar, Sachin S. Sapatnekar:
A new class of convex functions for delay modeling and itsapplication to the transistor sizing problem [CMOS gates]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(7): 779-788 (2000) - [c1]Mahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar:
Convex delay models for transistor sizing. DAC 2000: 655-660
Coauthor Index
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