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ORCIDYuanchao Xu 0002
Person information
- affiliation: Capital Normal University, Beijing, China
Other persons with the same name
- Yuanchao Xu 0001
![[0000-0003-4165-9138]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-4165-9138")
— North Carolina State University, Raleigh, NC, USA - Yuanchao Xu 0003 — SKL Computer Architecture, ICT CAS, Beijing, China
- Yuanchao Xu 0004 — Naval University of Engineering, Wuhan, China
- Yuanchao Xu 0005 — University of Manitoba, Winnipeg, Canada
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2020 – today
- 2023
[c20]Yuanchao Xu, Ruyi Qian, Yida Wang, Qirun Huo:
iNUMAlloc: Towards Intelligent Memory Allocation for AI Accelerators with NUMA. ISPA/BDCloud/SocialCom/SustainCom 2023: 929-936- [c19]Ruyi Qian, Mengjuan Gao, Qinwen Shi, Yuanchao Xu:
An Empirical Study of Memory Pool Based Allocation and Reuse in CUDA Graph. ICA3PP (5) 2023: 394-406 - [c18]Ruyi Qian, Bojun Cao, Mengjuan Gao, Qinwen Shi, Yida Wang, Yuanchao Xu, Qirun Huo, Keni Qiu:
EagerReuse: An Efficient Memory Reuse Approach for Complex Computational Graph. ICPADS 2023: 223-229 - 2022
- [c17]Jinyu Cheng, Ruyi Qian, Qinwen Shi, Gaomei Hu, Mengjuan Gao, Qirun Huo, Yuanchao Xu:
Towards Efficient Elastic Parallelism for Deep Learning Processor. ISPA/BDCloud/SocialCom/SustainCom 2022: 363-370 - 2021
- [c16]Jinyu Cheng, Kai Zhao, Yuanchao Xu:
Global-view based Task Migration for Deep Learning Processor. ISPA/BDCloud/SocialCom/SustainCom 2021: 908-915 - 2020
- [j7]Yazhu Lan, Kent W. Nixon, Qingli Guo, Guohe Zhang, Yuanchao Xu, Hai Li, Yiran Chen:
FCDM: A Methodology Based on Sensor Pattern Noise Fingerprinting for Fast Confidence Detection to Adversarial Attacks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(12): 4791-4804 (2020)
2010 – 2019
- 2019
- [j6]Keni Qiu, Yujie Zhu, Yuanchao Xu, Qirun Huo, Chun Jason Xue:
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. Microelectron. J. 83: 137-146 (2019) - [j5]Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang:
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Sustain. Comput. Informatics Syst. 22: 206-218 (2019) - [c15]Yazhu Lan, Qingli Guo, Guohe Zhang, Yuanchao Xu, Kent W. Nixon, Hai Helen Li, Yiran Chen:
Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks via Sensor Pattern Noise Fingerprinting. FPGA 2019: 188-189 - [c14]Yuanchao Xu, Yuanyuan Xu, Min Tang, Liangliang Zhang, Yazhu Lan:
Asymmetry & Locality-Aware Cache Bypass and Flush for NVM-Based Unified Persistent Memory. ISPA/BDCloud/SocialCom/SustainCom 2019: 168-175 - 2018
- [j4]Keni Qiu, Zhiyao Gong, Dongqin Zhou, Weiwen Chen, Yuanchao Xu, Xin Shi, Yongpan Liu:
Efficient energy management by exploiting retention state for self-powered nonvolatile processors. J. Syst. Archit. 87: 23-35 (2018) - [j3]Zeyi Hou, Hu Wan, Yuanchao Xu:
NMST: 一种基于线段树的持久性内存管理优化方法 (NMST: A Persistent Memory Management Optimization Approach Based on Segment Tree). 计算机科学 45(7): 78-83 (2018) - [c13]Keni Qiu, Weiwen Chen, Yuanchao Xu, Lixue Xia, Yu Wang, Zili Shao:
A peripheral circuit reuse structure integrated with a retimed data flow for low power RRAM crossbar-based CNN. DATE 2018: 1057-1062 - [c12]Dongqin Zhou, Keni Qiu, Yuanchao Xu, Xin Shi, Yongpan Liu:
A Dual-Threshold Scheme Along with Security Reinforcement for Energy Efficient Nonvolatile Processors. ISVLSI 2018: 70-75 - 2017
- [j2]Chun Xue, Keni Qiu, Weigong Zhang, Jing Wang, Yuanchao Xu, Mengying Zhao:
Data re-allocation enabled cache locking for embedded systems. J. Syst. Archit. 77: 3-13 (2017) - [c11]Yuanchao Xu, Zeyi Hou, Junfeng Yan, Lu Yang, Hu Wan:
i-BEP: A non-redundant and high-concurrency memory persistency model. DATE 2017: 618-621 - [c10]Yuanchao Xu, Lu Yang, Zeyi Hou, Qirun Huo, Keni Qiu:
Energy-Efficient Cache Management for NVM-Based IoT Systems. ISPA/IUCC 2017: 491-493 - [c9]Zhiyao Gong, Keni Qiu, Dongqin Zhou, Weiwen Chen, Yuanchao Xu, Xin Shi, Yongpan Liu:
Retention state-enabled and progress-driven energy management for self-powered nonvolatile processors. RTCSA 2017: 1-8 - [c8]Weiwen Chen, Keni Qiu, Jiqin Zhou, Yuanhui Ni, Yuanchao Xu:
Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus. TrustCom/BigDataSE/ICESS 2017: 839-843 - [c7]Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang:
Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. TrustCom/BigDataSE/ICESS 2017: 844-852 - 2016
- [j1]Yuanchao Xu, Hu Wan, Keni Qiu, Tao Li, Weigong Zhang:
Reducing Synchronization Cost for Single-Level Store in Mobile Systems. J. Comput. Sci. Technol. 31(4): 836-848 (2016) - [c6]Yuanchao Xu, Hu Wan, Zeyi Hou, Keni Qiu:
Mitigating sync overhead in single-level store systems. Conf. Computing Frontiers 2016: 188-196 - [c5]Keni Qiu, Junpeng Luo, Zhiyao Gong, Weigong Zhang, Jing Wang, Yuanchao Xu, Tao Li, Chun Jason Xue:
Refresh-aware loop scheduling for high performance low power volatile STT-RAM. ICCD 2016: 209-216 - [c4]Hu Wan, Youyou Lu, Yuanchao Xu, Jiwu Shu:
Empirical study of redo and undo logging in persistent memory. NVMSA 2016: 1-6 - [c3]Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang, Yuanchao Xu, Chun Jason Xue:
Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors. SAC 2016: 1710-1716 - [c2]Yuanchao Xu, Zeyi Hou:
NVM-Assisted Non-redundant Logging for Android Systems. Trustcom/BigDataSE/ISPA 2016: 1427-1433 - 2015
- [c1]Yuanchao Xu, Hu Wan, Lingjun Fan, Junfeng Yan:
Rethinking manycore caches for scale-out applications. IGSC 2015: 1-6
Coauthor Index
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