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"Balanced loop retiming to effectively architect STT-RAM-based hybrid cache ..."

Keni Qiu et al. (2016)

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DOI: 10.1145/2851613.2851670

access: closed

type: Conference or Workshop Paper

metadata version: 2020-08-05

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  - conf/sac/QiuZWZWXX16
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Keni Qiu, Weigong Zhang, Xiaoqiang Wu, Xiaoyan Zhu, Jing Wang, Yuanchao Xu, Chun Jason Xue:
Balanced loop retiming to effectively architect STT-RAM-based hybrid cache for VLIW processors. SAC 2016: 1710-1716

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