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ORCIDM. K. Venkatesha
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Journal Articles
- 2011
[j4]K. R. Radhika
, M. K. Venkatesha, G. N. Sekhar:
Signature authentication based on subpattern analysis. Appl. Soft Comput. 11(3): 3218-3228 (2011)- [j3]K. R. Radhika, M. K. Venkatesha, G. N. Sekhar:
A Novel Approach for Authentication of Online Handwritten Signature Based on residuals, poles and zeros. Int. J. Pattern Recognit. Artif. Intell. 25(1): 57-81 (2011) - [j2]K. R. Radhika, M. K. Venkatesha, G. N. Sekhar:
An approach for on-line signature authentication using Zernike moments. Pattern Recognit. Lett. 32(5): 749-760 (2011) - 2010
- [j1]K. R. Radhika, S. V. Sheela, M. K. Venkatesha, G. N. Sekhar:
Signature and Iris Authentication Based on Derived Kinematic Values. Int. J. Pattern Recognit. Artif. Intell. 24(8): 1237-1260 (2010)
Conference and Workshop Papers
- 2012
- [c3]M. J. Sudhamani, M. K. Venkatesha, K. R. Radhika:
Revisiting feature level and score level fusion techniques in multimodal biometrics system. ICMCS 2012: 881-885 - 2009
- [c2]K. R. Radhika, S. V. Sheela, M. K. Venkatesha, G. N. Sekhar:
Multi-modal Authentication Using Continuous Dynamic Programming. COST 2101/2102 Conference 2009: 228-235 - [c1]P. V. Manjunath, H. R. Baghyalakshmi, M. K. Venkatesha:
A Low-Power Low-Voltage CMOS Thyristor Based Delay Element. ICETET 2009: 135-140
Informal and Other Publications
- 2013
- [i2]Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi, M. K. Venkatesha:
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit. CoRR abs/1307.3690 (2013) - 2010
- [i1]H. R. Bhagyalakshmi, M. K. Venkatesha:
Optimized reversible BCD adder using new reversible logic gates. CoRR abs/1002.3994 (2010)
Coauthor Index
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