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H. R. Bhagyalakshmi

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2010 – 2019

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2013
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  - journals/corr/SaligramHKBV13
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Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A. Kulkarni, H. R. Bhagyalakshmi, M. K. Venkatesha:
Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit. CoRR abs/1307.3690 (2013)
2010
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H. R. Bhagyalakshmi, M. K. Venkatesha:
Optimized reversible BCD adder using new reversible logic gates. CoRR abs/1002.3994 (2010)

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