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2010 – 2019
- 2019
[j6]Ting-Sheng Chen
, Hung-Chi Kuo, An-Yeu Wu:
A 232-1996-kS/s Robust Compressive Sensing Reconstruction Engine for Real-Time Physiological Signals Monitoring. IEEE J. Solid State Circuits 54(1): 307-317 (2019)- [j5]Levent E. Aygun, Prakhar Kumar, Zhiwu Zheng, Ting-Sheng Chen, Sigurd Wagner, James C. Sturm, Naveen Verma:
Hybrid LAE-CMOS Force-Sensing System Employing TFT-Based Compressed Sensing for Scalability of Tactile Sensing Skins. IEEE Trans. Biomed. Circuits Syst. 13(6): 1264-1276 (2019) - [j4]Ching-Chun Liao, Ting-Sheng Chen, An-Yeu Wu:
Real-Time Multi-User Detection Engine Design for IoT Applications via Modified Sparsity Adaptive Matching Pursuit. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(8): 2987-3000 (2019) - [j3]Ting-Sheng Chen, Kai-Ni Hou, Win-Ken Beh, An-Yeu Wu:
Low-Complexity Compressed-Sensing-Based Watermark Cryptosystem and Circuits Implementation for Wireless Sensor Networks. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2485-2497 (2019) - [c6]Yu-Hsiang Chuang, Chang-Tzu Lin, Hung-Ming Chen, Chi-Han Lee, Ting-Sheng Chen:
More Effective Power Network Prototyping by Analytical and Centroid Learning. ISCAS 2019: 1-5 - [c5]Levent E. Aygun, Prakhar Kumar, Zhiwu Zheng, Ting-Sheng Chen, Sigurd Wagner, James C. Sturm, Naveen Verma:
Hybrid System for Efficient LAE-CMOS Interfacing in Large-Scale Tactile-Sensing Skins via TFT-Based Compressed Sensing. ISSCC 2019: 280-282 - 2018
- [j2]Sheng-Chun Kao, Ding-Yuan Lee, Ting-Sheng Chen, An-Yeu Wu:
Dynamically Updatable Ternary Segmented Aging Bloom Filter for OpenFlow-Compliant Low-Power Packet Processing. IEEE/ACM Trans. Netw. 26(2): 1004-1017 (2018) - [c4]Kai-Ni Hou, Ting-Sheng Chen, Hung-Chi Kuo, Tzu-Hsuan Chen, An-Yeu Wu:
Low-Complexity Secure Watermark Encryption for Compressed Sensing-Based Privacy Preserving. ICASSP 2018: 6408-6412 - [c3]Ting-Sheng Chen, Hung-Chi Kuo, An-Yeu Wu:
A 232-to-1996KS/s robust compressive-sensing reconstruction engine for real-time physiological signals monitoring. ISSCC 2018: 226-228 - 2017
- [c2]Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu:
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. VLSI-DAT 2017: 1-4 - 2016
- [j1]Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu:
Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing. IEEE Trans. Circuits Syst. I Regul. Pap. 63-I(10): 1661-1672 (2016) - 2010
- [c1]Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits. ASP-DAC 2010: 187-192
Coauthor Index
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