"Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for ..."

Chia-Heng Wu et al. (2017)

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DOI: 10.1109/VLSI-DAT.2017.7939641

access: closed

type: Conference or Workshop Paper

metadata version: 2017-06-20

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Chia-Heng Wu, Ting-Sheng Chen, Ding-Yuan Lee, Tsung-Te Liu, An-Yeu Wu:
Low-latency Voltage-Racing Winner-Take-All (VR-WTA) circuit for acceleration of learning engine. VLSI-DAT 2017: 1-4

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