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ORCIDChen-Chih Huang
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2010 – 2019
- 2015
[c15]Yen-Ting Lin, Shin-Chi Lai, Shin-Hao Chen, Shen-Yu Peng, Ke-Horng Chen
, Sheng Kang, Kevin Cheng, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee:
99.4% peak audio signal recovery rate and ultra-low 0.32dB matching error with 10Hz high resolution filter fitting wearable aided speech compensation system. A-SSCC 2015: 1-4- 2014
- [c14]Shin-Hao Chen, Shen-Yu Peng, Ke-Horng Chen, Shin-Chi Lai, Sheng Kang, Kevin Cheng, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee:
A 2.5W tablet speaker delivering 3.2W pseudo high power by psychoacoustic model based adaptive power management system. A-SSCC 2014: 221-224 - [c13]Wei-Chung Chen, Tzu-Chi Huang, Tsu-Wei Tsai, Ruei-Hong Peng, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Li-Ren Huang, Chao-Jen Huang, Chung-Chih Hung, Chin-Long Wey, Hsin-Yu Luo:
Single inductor quad output switching converter with priority-scheduled program for fast transient and unlimited-load range in 40nm CMOS technology. ESSCIRC 2014: 167-170 - [c12]Wei-Chung Chen, Kuei-Liang Lin, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang:
A pseudo fixed switching frequency 2kHz/A in optimum on-time control buck converter with predicting correction technique for EMI solution. ISCAS 2014: 946-949 - [c11]Shang-Hsien Yang, Yuan-Han Yang, Ke-Horng Chen, Chung-Chih Hung, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Huang Tian Hui:
A dual-level dual-phase pulse-width modulation class-D amplifier with 0.001% THD, 112 dB SNR. ISCAS 2014: 2676-2679 - [c10]Ying-Wei Chou, Meng-Wei Chien, Shin-Chieh Chen, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Zhih Han Tai, Yi Hsuan Cheng, Chi Chung Tsai, Hsin-Yu Luo, Shih-Ming Wang, Long-Der Chen, Cheng-Chen Yang, Huang Tian Hui:
A low THD clock-free Class-D audio amplifier with an increased damping resistor and cross offset cancellation technique. ISCAS 2014: 2680-2683 - [c9]Wei-Chung Chen, Yung-Sheng Huang, Meng-Wei Chien, Ying-Wei Chou, Hsin-Chieh Chen, Yi-Ping Su, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee:
±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems. VLSIC 2014: 1-2 - [c8]Tzu-Chi Huang, Ming-Jhe Du, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Jui-Lung Chen, Hung-Wei Chen:
A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency. VLSIC 2014: 1-2 - 2013
- [j8]Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee:
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement. IEEE J. Solid State Circuits 48(4): 1018-1030 (2013) - [j7]Shen-Yu Peng, Tzu-Chi Huang, Yu-Huei Lee, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Tsung-Yen Tsai, Chen-Chih Huang, Long-Der Chen, Cheng-Chen Yang:
Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings. IEEE J. Solid State Circuits 48(11): 2649-2661 (2013) - 2012
- [j6]Tzu-Chi Huang, Chun-Yu Hsieh, Yao-Yi Yang, Yu-Huei Lee, Yu-Chai Kang, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Ming-Wei Lee:
A Battery-Free 217 nW Static Control Power Buck Converter for Wireless RF Energy Harvesting With ά-Calibrated Dynamic On/Off Time and Adaptive Phase Lead Control. IEEE J. Solid State Circuits 47(4): 852-862 (2012) - [j5]Wen-Shen Chou, Tzu-Chi Huang, Yu-Huei Lee, Yao-Yi Yang, Yi-Ping Su, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Kuei-Ann Wen, Ying-Chih Hsu, Yung-Chow Peng, Fu-Lung Hsueh:
An Embedded Dynamic Voltage Scaling (DVS) System Through 55 nm Single-Inductor Dual-Output (SIDO) Switching Converter for 12-Bit Video Digital-to-Analog Converter. IEEE J. Solid State Circuits 47(7): 1568-1584 (2012) - [j4]Yu-Huei Lee, Chao-Chang Chiu, Shen-Yu Peng, Ke-Horng Chen, Ying-Hsi Lin, Chao-Cheng Lee, Chen-Chih Huang, Tsung-Yen Tsai:
A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management With Frequency-Based Control (FBC) for SoC System. IEEE J. Solid State Circuits 47(11): 2563-2575 (2012) - [c7]Yu-Huei Lee, Tzu-Chi Huang, Kuan-Yu Chu, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Tsung-Yen Tsai, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee:
A single-inductor dual-output (SIDO) based power management with adaptive bus voltage modulation and zero cross-regulation in 40nm CMOS. ESSCIRC 2012: 161-164 - [c6]Yi-Ping Su, Shao-Wei Chiu, Chun-Chieh Kuo, Yu-Huei Lee, Ke-Horng Chen, Ying-Hsi Lin, Chen-Chih Huang, Chao-Cheng Lee, Yu-Wen Chen:
Inductorless and electrolytic capacitorless pseudo-sine current controller in LED lighting system with 1.1W/2.2W power reduction. ESSCIRC 2012: 442-445 - [c5]Yu-Huei Lee, Shen-Yu Peng, Alex Chun-Hsien Wu, Chao-Chang Chiu, Yao-Yi Yang, Ming-Hsin Huang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Ching-Yuan Yeh, Chen-Chih Huang, Chao-Cheng Lee:
A 50nA quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40nm CMOS for 5.6 times MIPS performance. VLSIC 2012: 178-179 - 2011
- [j3]Yu-Huei Lee, Yao-Yi Yang, Shih-Jung Wang, Ke-Horng Chen, Ying-Hsi Lin, Yi-Kuang Chen, Chen-Chih Huang:
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency. IEEE J. Solid State Circuits 46(4): 904-915 (2011) - [j2]Yu-Huei Lee, Tzu-Chi Huang, Yao-Yi Yang, Wen-Shen Chou, Ke-Horng Chen, Chen-Chih Huang, Ying-Hsi Lin:
Minimized Transient and Steady-State Cross Regulation in 55-nm CMOS Single-Inductor Dual-Output (SIDO) Step-Down DC-DC Converter. IEEE J. Solid State Circuits 46(11): 2488-2499 (2011) - [c4]Yu-Huei Lee, Chao-Chang Chiu, Ke-Horng Chen, Ying-Hsi Lin, Chen-Chih Huang:
On-the-fly dynamic voltage scaling (DVS) in 65nm energy-efficient power management with frequency-based control (FBC) for SoC system. A-SSCC 2011: 329-332 - 2010
- [j1]Yu-Huei Lee, Yao-Yi Yang, Ke-Horng Chen, Ying-Hsi Lin, Shih-Jung Wang, Kuo-Lin Zheng, Po-Fung Chen, Chun-Yu Hsieh, Yu-Zhou Ke, Yi-Kuang Chen, Chen-Chih Huang:
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System. IEEE J. Solid State Circuits 45(11): 2227-2238 (2010)
2000 – 2009
- 2009
- [c3]Yu-Huei Lee, Shih-Jung Wang, Yao-Yi Yang, Kuo-Lin Zheng, Po-Fung Chen, Chun-Yu Hsieh, Ming-Hsin Huang, Yu-Nong Tsai, Yu-Zhou Ke, Ke-Horng Chen, Yi-Kuang Chen, Chen-Chih Huang, Ying-Hsi Lin:
A high efficiency and compact size 65nm power management module with 1.2v low-voltage PWM controller for UWB system application. ESSCIRC 2009: 272-275 - 2007
- [c2]Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee:
A 10b 200MS/s pipelined folding ADC with offset calibration. ESSCIRC 2007: 151-154 - [c1]Cheng-Chung Hsu, Fong-Ching Huang, Chih-Yung Shih, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Behzad Razavi:
An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration. ISSCC 2007: 464-615
Coauthor Index
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