"A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated ..."

Yu-Huei Lee et al. (2013)

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DOI: 10.1109/JSSC.2013.2237991

access: closed

type: Journal Article

metadata version: 2020-08-30

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Yu-Huei Lee, Shen-Yu Peng, Chao-Chang Chiu, Alex Chun-Hsien Wu, Ke-Horng Chen, Ying-Hsi Lin, Shih-Wei Wang, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee:
A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement. IEEE J. Solid State Circuits 48(4): 1018-1030 (2013)

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