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ORCIDCarsten Tradowsky
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2010 – 2019
- 2017
[c15]Manuel Mohr, Carsten Tradowsky:
Pegasus: Efficient data transfers for PGAS languages on non-cache-coherent many-cores. DATE 2017: 1781-1786- [c14]Tanja Harbaum
, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker:
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC 2017: 153-158 - 2016
- [b1]Carsten Tradowsky:
Methoden zur applikationsspezifischen Effizienzsteigerung adaptiver Prozessorplattformen. Karlsruhe Institute of Technology, Germany, 2016 - [c13]Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker:
A Dynamic Cache Architecture for Efficient Memory Resource Allocation in Many-Core Systems. ARC 2016: 343-351 - [c12]Carsten Tradowsky, Enrique Cordero, Christoph Orsinger, Malte Vesper, Jürgen Becker:
Adaptive Cache Structures. ARCS 2016: 87-99 - 2015
- [c11]Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker:
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. ARC 2015: 103-114 - [c10]Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker:
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. ARC 2015: 311-320 - 2014
- [c9]Carsten Tradowsky, Martin Schreiber, Malte Vesper, Ivan Domladovec, Maximilian Braun, Hans-Joachim Bungartz, Jürgen Becker:
Towards Dynamic Cache and Bandwidth Invasion. ARC 2014: 97-107 - [c8]Carsten Tradowsky, Tobias Gädeke, Thomas Bruckschlögl, Wilhelm Stork, Klaus D. Müller-Glaser, Jürgen Becker:
SmartLoCore: A Concept for an Adaptive Power-Aware Localization Processor. PDP 2014: 478-481 - 2013
- [c7]Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker:
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. ISSoC 2013: 1-8 - [c6]Carsten Tradowsky, Tanja Harbaum, Shaver Deyerle, Jürgen Becker:
LImbiC: An adaptable architecture description language model for developing an application-specific image processor. ISVLSI 2013: 34-39 - 2012
- [c5]Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker:
On Dynamic Run-time Processor Pipeline Reconfiguration. IPDPS Workshops 2012: 419-424 - [c4]Carsten Tradowsky, Enrique Cordero, Thorsten Deuser, Michael Hübner, Jürgen Becker:
Determination of on-chip temperature gradients on reconfigurable hardware. ReConFig 2012: 1-8 - [c3]Michael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg Henkel, Jürgen Becker:
Adaptive processor architecture - invited paper. ICSAMOS 2012: 244-251 - [c2]Carsten Tradowsky, Florian Thoma, Michael Hübner, Jürgen Becker:
LISPARC: Using an architecture description language approach for modelling an adaptive processor microarchitecture. SIES 2012: 279-282 - 2011
- [c1]Michael Hübner, Carsten Tradowsky, Diana Göhringer, Lars Braun, Florian Thoma, Jörg Henkel, Jürgen Becker:
Dynamic Processor Reconfiguration. ReConFig 2011: 123-128
Coauthor Index
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