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Koichi Tachikake

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Journal Articles

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2005
[j2]
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Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition. IEICE Trans. Inf. Syst. 88-D(7): 1340-1349 (2005)
2003
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Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
A Hardware/Software Partitioning Algorithm for Processor Cores with Packed SIMD-Type Instructions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3218-3224 (2003)

Conference and Workshop Papers

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2004
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Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo Ohtsuki:
Instruction set and functional unit synthesis for SIMD processor cores. ASP-DAC 2004: 743-750
2003
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Koichi Tachikake, Nozomu Togawa, Yuichiro Miyaoka, Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki:
A hardware/software partitioning algorithm for SIMD processor cores. ASP-DAC 2003: 135-140

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