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ORCIDTakeshi Ueno
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2020 – today
- 2023
[j12]Shusuke Kawai
, Takeshi Ueno, Hiroki Ishikuro, Kohei Onizuka:
An Active Slew Rate Control Gate Driver IC With Robust Discrete-Time Feedback Technique for 600-V Superjunction MOSFETs. IEEE J. Solid State Circuits 58(2): 428-438 (2023)
2010 – 2019
- 2019
- [c7]Shusuke Kawai, Takeshi Ueno, Kohei Onizuka:
A 4.5V/ns Active Slew-Rate-Controlling Gate Driver with Robust Discrete-Time Feedback Technique for 600V Superjunction MOSFETs. ISSCC 2019: 252-254 - 2016
- [c6]Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura:
20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting. A-SSCC 2016: 9-12 - 2012
- [j11]Shohei Hido, Shoko Suzuki, Risa Nishiyama, Takashi Imamichi, Rikiya Takahashi, Tetsuya Nasukawa, Tsuyoshi Idé, Yusuke Kanehira, Rinju Yohda, Takeshi Ueno, Akira Tajima, Toshiya Watanabe:
Modeling Patent Quality: A System for Large-scale Patentability Analysis using Text Mining. Inf. Media Technol. 7(3): 1180-1191 (2012) - [j10]Shohei Hido, Shoko Suzuki, Risa Nishiyama, Takashi Imamichi, Rikiya Takahashi, Tetsuya Nasukawa, Tsuyoshi Idé, Yusuke Kanehira, Rinju Yohda, Takeshi Ueno, Akira Tajima, Toshiya Watanabe:
Modeling Patent Quality: A System for Large-scale Patentability Analysis using Text Mining. J. Inf. Process. 20(3): 655-666 (2012) - 2010
- [j9]Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
A Direct Conversion Receiver Adopting Balanced Three-Phase Analog System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 367-374 (2010)
2000 – 2009
- 2008
- [j8]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 454-460 (2008) - [j7]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. IEICE Trans. Electron. 91-C(6): 887-893 (2008) - [c5]Masanori Furuta, Takafumi Yamaji, Takeshi Ueno, Tetsuro Itakura:
An area-efficient sampling rate converter using negative feedback technique. ISCAS 2008: 1922-1925 - 2007
- [j6]Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
A 1.2-V, 12-bit, 200 MSample/s Current-Steering D/A Converter in 90-nm CMOS. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(2): 365-371 (2007) - 2006
- [j5]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(7): 2003-2008 (2006) - [j4]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid State Circuits 41(7): 1589-1595 (2006) - [c4]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. CICC 2006: 501-504 - [c3]Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni:
Balanced 3-phase analog signal processing for radio communications. ISCAS 2006 - 2005
- [j3]Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. IEICE Electron. Express 2(15): 429-433 (2005) - [j2]Takeshi Ueno, Tetsuro Itakura:
A 0.9 V 1.5 mW Continuous-Time Modulator for W-CDMA. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(2): 461-468 (2005) - [c2]Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
A 1.2-V, 12-bit, 200M sample/s current-steering D/A converter in 90-nm CMOS. CICC 2005: 747-750 - [c1]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. ESSCIRC 2005: 527-530 - 2002
- [j1]Takeshi Ueno, Akira Yasuda, Takafumi Yamaji, Tetsuro Itakura:
A fourth-order bandpass Δ-Σ modulator using second-order bandpass noise-shaping dynamic element matching. IEEE J. Solid State Circuits 37(7): 809-816 (2002)
Coauthor Index
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