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ORCIDYosuke Toyama
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2010 – 2019
- 2019
[j1]Yosuke Toyama
, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka:
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators. IEEE J. Solid State Circuits 54(10): 2730-2742 (2019)- 2018
- [c5]Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka:
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications. A-SSCC 2018: 1-4 - [c4]Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. VLSI Circuits 2018: 263-264 - [i1]Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators. CoRR abs/1808.09335 (2018) - 2016
- [c3]Yosuke Toyama, Taichi Ogawa, Takeshi Ueno, Tetsuro Itakura:
20 mV input, 4.2 V output SIDO boost converter with low-power controller and adaptive switch size selector for thermoelectric energy harvesting. A-SSCC 2016: 9-12 - [c2]Kohei Yamada, Yosuke Toyama, Hiroki Ishikuro:
A programmable ΔΣ SAR-ADC with charge shuttling technique. ISOCC 2016: 51-52 - 2013
- [c1]Kentaro Yoshioka, Yosuke Toyama, Teruo Jyo, Hiroki Ishikuro:
A voltage scaling 0.25-1.8 V delta-sigma modulator with inverter-opamp self-configuring amplifier. ISCAS 2013: 809-812
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