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2010 – 2019
- 2015
[i1]Brian L. Ji, H. Li, Q. Ye, S. Gausepohl, S. Deora, Dmitry Veksler, S. Vivekanand, H. Chong, H. Stamper, T. Burroughs, C. Johnson, M. Smalley, S. Bennett, V. Kaushik, J. Piccirillo, M. Rodgers, M. Passaro, M. Liehr:
In-Line-Test of Variability and Bit-Error-Rate of HfOx-Based Resistive Memory. CoRR abs/1509.00070 (2015)- 2010
- [j4]Leland Chang, David J. Frank, Robert K. Montoye, Steven J. Koester
, Brian L. Ji, Paul W. Coteus, Robert H. Dennard, Wilfried Haensch:
Practical Strategies for Power-Efficient Computing Technologies. Proc. IEEE 98(2): 215-236 (2010)
2000 – 2009
- 2006
- [j3]Kerry Bernstein, David J. Frank, Anne E. Gattiker, Wilfried Haensch, Brian L. Ji, Sani R. Nassif, Edward J. Nowak, Dale J. Pearson, Norman J. Rohrer:
High-performance CMOS variability in the 65-nm regime and beyond. IBM J. Res. Dev. 50(4-5): 433-450 (2006) - 2005
- [j2]Troy J. Beukema, Michael Sorna, Karl Selander, Steven Zier, Brian L. Ji, Phil Murfet, James Mason, Woogeun Rhee, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes:
A 6.4-Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization. IEEE J. Solid State Circuits 40(12): 2633-2645 (2005)
1990 – 1999
- 1998
- [j1]Toshiaki Kirihata, Martin Gall, Kohji Hosokawa, Jean-Marc Dortu, Hing Wong, Peter Pfefferl, Brian L. Ji, Oliver Weinfurtner, John K. DeBrosse, Hartmud Terletzki, Manfred Selz, Wayne Ellis, Matthew R. Wordeman, Oliver Kiehl:
A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. IEEE J. Solid State Circuits 33(11): 1711-1719 (1998)
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