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ORCIDTerrence S. T. Mak
- > Home > Persons > Terrence S. T. Mak
Publications
- 2013
[j12]Ra'ed Al-Dujaily, Terrence S. T. Mak, Kai-Pui Lam, Fei Xia, Alex Yakovlev
, Chi-Sang Poon:
Dynamic On-Chip Thermal Optimization for Three-Dimensional Networks-On-Chip. Comput. J. 56(6): 756-770 (2013)- 2011
- [j3]Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk:
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58(8): 3701-3716 (2011) - [c23]Ra'ed Al-Dujaily, Terrence S. T. Mak, Kuan Zhou, Kai-Pui Lam, Yicong Meng, Alexandre Yakovlev, Chi-Sang Poon:
On-chip dynamic programming networks using 3D-TSV integration. ICSAMOS 2011: 318-325 - [c22]Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon:
Comparative ODE benchmarking of unidirectional and bidirectional DP networks for 3D-IC. VLSI-SoC 2011: 98-101 - [c20]Kai-Pui Lam, Terrence S. T. Mak, Chi-Sang Poon:
Cycle avoidance in 2D/3D bidirectional graphs using shortest-path dynamic programming network. VLSI-SoC 2011: 354-358 - 2010
- [j1]Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon:
A CMOS Current-Mode Dynamic Programming Circuit. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(12): 3112-3123 (2010) - 2009
- [c18]Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 - 2007
- [c11]Terrence S. T. Mak, Kai-Pui Lam, H. S. Ng, Guy Rachmuth, Chi-Sang Poon:
A Current-Mode Analog Circuit for Reinforcement Learning Problems. ISCAS 2007: 1301-1304 - [c10]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS 2007: 173-182 - 2004
- [c8]Terrence S. T. Mak, Kai-Pui Lam:
Embedded Computation of Maximum-Likelihood Phylogeny Inference Using Platform FPGA. CSB 2004: 512-514 - [c7]Terrence S. T. Mak, Kai-Pui Lam:
FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. FPL 2004: 1076-1079 - [c6]Terrence S. T. Mak, Kai-Pui Lam:
On Computing Maximum Likelihood Phylogeny Using FPGA p. FPL 2004: 1188 - 2003
- [c5]Terrence S. T. Mak, Kai-Pui Lam:
High Speed GAML-based Phylogenetic Tree Reconstruction Using HW/SW Codesign. CSB 2003: 470-473 - [c4]Kai-Pui Lam, Sui-Tung Mak:
An FPGA-based eigenfilter using fast Hebbian learning. ICASSP (2) 2003: 765-768 - [c3]H. S. Ng, Sui-Tung Mak, Kai-Pui Lam:
Field programmable gate arrays and analog implementation of BRIN for optimization problems. ISCAS (5) 2003: 73-76 - 2002
- [c2]Kai-Pui Lam, Sui-Tung Mak:
On Computing Transitive-Closure Equivalence Sets Using a Hybrid GA-DP Approach. FPL 2002: 935-944 - [c1]Sui-Tung Mak, Kai-Pui Lam:
Serial-parallel tradeoff analysis of all-pairs shortest path algorithms in reconfigurable computing. FPT 2002: 302-305
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