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ORCIDTsutomu Yoshimura
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2020 – today
- 2023
[c16]Ryuji Komabayashi, Tsutomu Yoshimura:
Analysis of the Electromagnetic Coupling of Two Phase-Locked Loops. ISCAS 2023: 1-4- 2022
- [j11]Tsutomu Yoshimura
:
Self-Coupling and Mutual Pulling in Phase-Locked Loops. IEEE Trans. Circuits Syst. I Regul. Pap. 69(8): 3260-3271 (2022) - 2021
- [j10]Tsutomu Yoshimura:
Study of Injection Pulling of Oscillators in Phase-Locked Loops. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 321-332 (2021) - [c15]Tsutomu Yoshimura:
Mitigation of Mutual Pulling in Two Phase-locked Loops. NEWCAS 2021: 1-4
2010 – 2019
- 2019
- [j9]Takao Kihara, Tomoya Takahashi, Tsutomu Yoshimura:
Digital Mismatch Correction for Bandpass Sampling Four-Channel Time-Interleaved ADCs in Direct-RF Sampling Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2007-2016 (2019) - [c14]Takao Kihara, Keisuke Miyakoshi, Tsutomu Yoshimura:
Digital Third-Order Nonlinearity Correction for Time-Interleaved A/D Converters with VCOs. ISCAS 2019: 1-4 - 2018
- [c13]Fukuyama Tokuya, Takao Kihara, Tsunehiro Yoshio, Tsutomu Yoshimura:
A Standard-cell Based A/D Converter with a Back-gate VCO and a Fat Tree Encoder. APCCAS 2018: 22-25 - [c12]Yuma Isobe, Takao Kihara, Tsutomu Yoshimura:
A Polyphase Decimation Filter for Time-Interleaved ADCs in Direct-RF Sampling Receivers. APCCAS 2018: 163-166 - [c11]Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura:
Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL. APCCAS 2018: 175-178 - [c10]Hiroyuki Kobayashi, Kazuo Kumamoto, Tsutomu Yoshimura, Toshio Haga, Muneyoshi Iyota, Makoto Katoh:
A Design of Engineering PBL on Embedded System for Novice Freshmen Students. TENCON 2018: 782-786 - 2017
- [c9]Tomoya Takahashi, Takao Kihara, Tsutomu Yoshimura:
Digital correction of mismatches in time-interleaved ADCs for digital-RF receivers. ICECS 2017: 9-12 - [c8]Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura:
Spur reduction by self-injection loop in a fractional-N PLL. ICECS 2017: 260-263 - [c7]Takao Kihara, Hiroyuki Yano, Tsutomu Yoshimura:
Design of cascaded integrator-comb decimation filters for direct-RF sampling receivers. ISCAS 2017: 1-4 - 2016
- [c6]Masahiro Hiramori, Ryota Bandou, Shuhei Iwade, Hiroshi Makino, Tsutomu Yoshimura, Yoshio Matsuda:
A study on fast motion estimation algorithm. GCCE 2016: 1-3 - [c5]Naohiro Fujii, Shuei Morishita, Takao Kihara, Tsutomu Yoshimura:
A 2.6GHz subharmonically injection-locked PLL with low-spur and wide-lock-range injection. NEWCAS 2016: 1-4 - [c4]Takao Kihara, Shigesato Matsuda, Tsutomu Yoshimura:
Analysis and design of differential LNAs with on-chip transformers in 65-nm CMOS technology. NEWCAS 2016: 1-4 - 2015
- [c3]Shuei Morishita, Shinji Shimizu, Takao Kihara, Tsutomu Yoshimura:
Subharmonically injection-locked PLL with variable pulse-width injections. ISCAS 2015: 557-560 - 2014
- [j8]Shunji Nakata, Hiroshi Makino, Junpei Hosokawa, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Energy Efficient Stepwise Charging of a Capacitor Using a DC-DC Converter With Consecutive Changes of its Duty Ratio. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(7): 2194-2203 (2014) - [c2]Shinji Shimizu, Junki Mizuno, Shuei Morishita, Koichiro Hida, Tsutomu Yoshimura:
Analysis and modeling of oscillators with interference noise. ICECS 2014: 128-131 - 2013
- [j7]Tsutomu Yoshimura, Shuhei Iwade, Hiroshi Makino, Yoshio Matsuda:
Analysis of Pull-in Range Limit by Charge Pump Mismatch in a Linear Phase-Locked Loop. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(4): 896-907 (2013) - 2012
- [j6]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Utilising the normal distribution of the write noise margin to easily predict the SRAM write yield. IET Circuits Devices Syst. 6(4): 260-270 (2012) - 2011
- [j5]Hiroshi Makino, Shunji Nakata, Hirotsugu Suzuki, Shin'ichiro Mutoh, Masayuki Miyama, Tsutomu Yoshimura, Shuhei Iwade, Yoshio Matsuda:
Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution. IEEE Trans. Circuits Syst. II Express Briefs 58-II(4): 230-234 (2011)
2000 – 2009
- 2006
- [j4]Tsutomu Yoshimura, Atsushi Iwata:
A study of interference in synchronous systems. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(8): 1726-1740 (2006) - 2004
- [j3]Tsutomu Yoshimura, Atsushi Iwata:
An analysis of interference in synchronous systems. IEICE Electron. Express 1(15): 465-471 (2004) - 2002
- [c1]Tsutomu Yoshimura, Kimio Ueda, Jun Takasoh, Yoshiki Wada, Toshihide Oka, Harufusa Kondoh, Osamu Chiba, Yoshihumi Azekawa, Masahiko Ishiwaki:
A 10Gbase Ethernet transceiver (LAN PHY) in a 1.8 V, 0.18 μm SOI/CMOS technology. CICC 2002: 355-358
1990 – 1999
- 1999
- [j2]Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999) - 1996
- [j1]Tsutomu Yoshimura, Harufusa Kondoh, Yoshio Matsuda, Tadashi Sumi:
A 622-Mb/s bit/frame synchronizer for high-speed backplane data communication. IEEE J. Solid State Circuits 31(7): 1063-1066 (1996)
Coauthor Index
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