Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM ..."

Yasunobu Nakase et al. (1999)

> Home

Details and statistics

DOI: 10.1109/4.753682

access: closed

type: Journal Article

metadata version: 2022-07-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/jssc/NakaseMPKCSYWMK99
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/jssc/NakaseMPKCSYWMK99
Yasunobu Nakase, Yoshikazu Morooka, David J. Perlman, Daniel J. Kolor, Jae-Myoung Choi, Hyun J. Shin, Tsutomu Yoshimura, Naoya Watanabe, Yoshio Matsuda, Masaki Kumanoya, Michihiro Yamada:
Source-synchronization and timing vernier techniques for 1.2-GB/s SLDRAM interface. IEEE J. Solid State Circuits 34(4): 494-501 (1999)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.