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Darren Anand
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Journal Articles
- 2011
- [j5]Darren Anand, Kevin W. Gorman, Mark Jacunski, Adrian Paparelli
:
Embedded DRAM in 45-nm Technology and Beyond. IEEE Des. Test Comput. 28(1): 14-21 (2011) - 2005
- [j4]John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli
, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40(1): 213-222 (2005) - 2003
- [j3]Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater:
An On-Chip Self-Repair Calculation and Fusing Methodology. IEEE Des. Test Comput. 20(5): 67-75 (2003) - [j2]Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier:
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38(11): 1974-1980 (2003) - 2002
- [j1]John E. Barth Jr., Jeffrey H. Dreibelbis, Eric A. Nelson, Darren Anand, Gary Pomichter, Peter Jakobsen, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM design and architecture for the IBM 0.11-µm ASIC offering. IBM J. Res. Dev. 46(6): 675-690 (2002)
Conference and Workshop Papers
- 2019
- [c8]Eric Hunt-Schroeder, Darren Anand, Edward Hwang, Aaron Cummings, Matthew Deming, Michael Roberge, Michael Ziegerhofer:
Behavioral Modeling of a Charge Trap Transistor One Time Programmable Memory. NATW 2019: 1-6 - 2018
- [c7]Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata:
14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. VLSI Circuits 2018: 87-88 - 2010
- [c6]Mark Jacunski, Darren Anand, Robert Busch, John A. Fifield, Matthew Lanahan, Paul Lane, Adrian Paparelli
, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 45nm SOI compiled embedded DRAM with random cycle times down to 1.3ns. CICC 2010: 1-4 - 2007
- [c5]Darren Anand, Jim Covino, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Mark Jacunski, Jake Paparelli, Gary Pomichter, Dale E. Pontius, Michael Roberge, Stephen Sliva:
A 1.0GHz multi-banked embedded DRAM in 65nm CMOS featuring concurrent refresh and hierarchical BIST. CICC 2007: 795-798 - 2006
- [c4]Kevin W. Gorman, Darren Anand, Gary Pomichter, William R. Corbin:
Low Cost Test of High Bandwidth Embedded Memories. CICC 2006: 445-448 - 2004
- [c3]Michael R. Nelms, Kevin W. Gorman, Darren Anand:
Generating At-Speed Array Fail Maps with Low-Speed ATE. VTS 2004: 87-96 - 2001
- [c2]Michael R. Ouellette, Darren Anand, Peter Jakobsen:
Shared fuse macro for multiple embedded memory devices with redundancy. CICC 2001: 191-194 - [c1]Peter Jakobsen, Jeffrey H. Dreibelbis, Gary Pomichter, Darren Anand, John Barth, Michael R. Nelms, Jeffrey Leach, George M. Belansek:
Embedded DRAM built in self test and methodology for test insertion. ITC 2001: 975-984
Coauthor Index
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