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ORCIDSteven Burns 0001
Person information
- affiliation: Globalfoundries, Essex Junction, VT, USA
- affiliation: IBM Systems and Technology Group, Poughkeepsie, NY, USA
Other persons with the same name
- Steven Burns — disambiguation page
- Steven Burns 0002 — Burns Industries Inc., Nashua, NH, USA
- Steven M. Burns (aka: Steve Burns 0002, Steven Morgan Burns) — Intel Corporation, Hillsboro, OR, USA (and 1 more)
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2010 – 2019
- 2017
[c3]Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns:
12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%. ISSCC 2017: 212-213- 2016
- [j3]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan
, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar A. Khan, Toshiaki Kirihata, Subramanian S. Iyer:
A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access. IEEE J. Solid State Circuits 51(1): 230-239 (2016) - 2015
- [c2]Gregory Fredeman, Donald W. Plass, Abraham Mathews, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns:
17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access. ISSCC 2015: 1-3 - 2012
- [c1]John Barth, Don Plass, Adis Vehabovic, Rajiv V. Joshi, Rouwaida Kanj, Steven Burns, Todd Weaver:
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro. VLSIC 2012: 110-111
2000 – 2009
- 2005
- [j2]John E. Barth Jr., Darren Anand, Steve Burns, Jeffrey H. Dreibelbis, John A. Fifield, Kevin W. Gorman, Michael R. Nelms, Erik Nelson, Adrian Paparelli, Gary Pomichter, Dale E. Pontius, Stephen Sliva:
A 500-MHz multi-banked compilable DRAM macro with direct write and programmable pipelining. IEEE J. Solid State Circuits 40(1): 213-222 (2005) - 2003
- [j1]Harold Pilo, Darren Anand, John Barth, Steve Burns, Phil Corson, Jim Covino, Steve Lamphier:
A 5.6-ns random cycle 144-Mb DRAM with 1.4 Gb/s/pin and DDR3-SRAM interface. IEEE J. Solid State Circuits 38(11): 1974-1980 (2003)
Coauthor Index
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last updated on 2024-04-25 01:25 CEST by the dblp team
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