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ORCIDToshiyuki Kouchi
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Journal Articles
- 2021
[j1]Toshiyuki Kouchi
, Mami Kakoi, Noriyasu Kumazaki, Akio Sugahara, Akihiro Imamoto, Yasufumi Kajiyama, Yuri Terada, Sanad Bushnaq, Naoaki Kanagawa, Takuyo Kodama, Ryo Fukuda, Hiromitsu Komai, Norichika Asaoka, Hidekazu Ohnishi, Ryosuke Isomura, Takaya Handa, Kensuke Yamamoto, Yuki Ishizaki, Yoko Deguchi, Atsushi Okuyama, Junichi Sato, Hiroki Yabe, Cynthia Hsu, Masahiro Yoshihara:
A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs. IEEE J. Solid State Circuits 56(1): 225-234 (2021)
Conference and Workshop Papers
- 2023
- [c3]Mario Sako, T. Nakajima, Fumihiro Kono, T. Nakano, Masaki Fujiu, Junji Musha, Dai Nakamura, Naoaki Kanagawa, Y. Shimizu, Kosuke Yanagidaira, Tetsuaki Utsumi, T. Kawano, Yoshikazu Hosomura, Hiroki Yabe, M. Kano, Hiroshi Sugawara, A. H. Sravan, K. Hayashi, Toshiyuki Kouchi, Y. Watanabe:
A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm2 bit density with 3.2Gbps interface and 205MB/s program throughput. VLSI Technology and Circuits 2023: 1-2 - 2020
- [c2]Toshiyuki Kouchi, Noriyasu Kumazaki, Masashi Yamaoka, Sanad Bushnaq, Takuyo Kodama, Yuki Ishizaki, Yoko Deguchi, Akio Sugahara, Akihiro Imamoto, Norichika Asaoka, Ryosuke Isomura, Takaya Handa, Junichi Sato, Hiromitsu Komai, Atsushi Okuyama, Naoaki Kanagawa, Yasufumi Kajiyama, Yuri Terada, Hidekazu Ohnishi, Hiroki Yabe, Cynthia Hsu, Mami Kakoi, Masahiro Yoshihara:
13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs. ISSCC 2020: 226-228 - 2001
- [c1]Ryo Haga, Tetsuya Kaneko, Atsushi Nakayama, Shinji Miyano, Hiroyuki Takenaka, Kenji Numata, Hiroyuki Koinuma, Takehiko Hojo, Akikuni Sato, Toshiyuki Kouchi, Kenichiro Mimoto, Masaaki Tazawa, Tsutomu Ohkubo, Takanori Andou, Tetsuya Amano:
Interface socket design methodology to generate embedded DRAM macros. CICC 2001: 537-540
Coauthor Index
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