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ORCIDXing Li 0023
Person information
- affiliation: Huawei Noah's Ark Lab, Huawei, Hong Kong, SAR, China
Other persons with the same name
- Xing Li — disambiguation page
- Xing Li 0001
![[0000-0003-1260-8657]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-1260-8657")
— Tsinghua University, Department of Electronic Engineering, China (and 1 more) - Xing Li 0002 — Nanjing University of Information Science and Technology, KLME / ILCEC / CIC-FEMD, China
- Xing Li 0003 — FU Berlin, Germany
- Xing Li 0004 — Broadcom, Irvine, CA, USA (and 1 more)
- Xing Li 0005 — Nanjing Forestry University, College of Information Science and Technology, College of Artificial intelligence, China (and 1 more)
- Xing Li 0006 — Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
- Xing Li 0007 — Alibaba Group, Hangzhou, China
- Xing Li 0008 — Southwest University, Chongqing, China
- Xing Li 0009 — Chongqing University, Chongqing, China
- Xing Li 0010 — Sun Yat-sen University, Guangzhou, China
- Xing Li 0011 — Technische Universität, Berlin, Germany
- Xing Li 0012 — Central South University, Changsha, Hunan, China
- Xing Li 0013 — National Digital Switching System Engineering and Technological Research Center, Zhengzhou, China
- Xing Li 0014 — Beihang University, Beijing, China
- Xing Li 0015 — Shanghai University, Shanghai, China
- Xing Li 0016 — China Tobacco Guangxi Industrial CO.,LTD., China
- Xing Li 0017 — Chongqing University, Chongqing, China
- Xing Li 0018 — Siemens Gamesa Renewable Energy, Brande, Denmark
- Xing Li 0019 — Institute of Microelectronics, Chinese Academy of Sciences, Beijing, China
- Xing Li 0020 — Central South University, Changsha, China
- Xing Li 0021 — Beijing Institute of Tracking and Telecommunication Technology, Beijing, China
- Xing Li 0022 — Jiangsu Normal University, Xuzhou, Jiangsu, China
- Xing Li 0024 — Guilin University of Electronic Technology, China
- Xing Li 0025 — China Communications Services Sci and Tech Co., Ltd., Wuhan, China
- Xing Li 0026 — King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia
- Xing Li 0027 — Xi'an Jiaotong University, Xi'an, China
- Xing Li 0028 — Sun Yat-sen University, Guangzhou, China
- Xing Li 0029 — Beihang University, Beijing, China
- Xing Li 0030 — Jianghan University, Wuhan, Hubei, China
- Xing Li 0031 — Shanghai Jiao Tong University, Shanghai, China
- Xing Li 0032 — Hubei University of Technology, Wuhan, China
- Xing Li 0033 — Institute of Water Resources and Hydropower, Sichuan University, China
- Xing Li 0034 — Nanjing University of Science and Technology, Nanjing, China
- Xing Li 0035 — Nanjing Hydraulic Research Institute, Nanjing, China
- Xing Li 0036 — Southern Medical University, Guangzhou, China
- Xing Li 0037 — School of Management, Xi'an University of Architecture and Technology, Xi'an, China
- Xing Li 0038 — Sino-Dutch Joint Laboratory of Horticultural Genomics, Institute of Vegetables and Flowers, Chinese Academy of Agricultural Sciences, Beijing, China
- Xing Li 0039 — Dongguan University of Technology, Dongguan, China
- Xing Li 0040 — Northwestern Polytechnical University, Xi'an, China (and 1 more)
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2020 – today
- 2025
[j2]Tianji Liu, Yang Sun, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young:
A Unified Parallel Framework for LUT Mapping and Logic Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(1): 214-226 (2025)- [j1]Junfeng Liu, Liwei Ni, Lei Chen, Xing Li, Qinghua Zhao, Xingquan Li, Shuai Ma:
A Delay-Driven Iterative Technology Mapping Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 44(7): 2585-2598 (2025) - [c19]Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva:
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization. ASP-DAC 2025: 72-78 - [c18]Ruofei Tang, Xuliang Zhu, Xinyi Zhang, Lei Chen, Xing Li, Mingxuan Yuan, Jianliang Xu:
EDGE: DBMS-Empowered Boolean Decomposition for GIG Synthesis. DAC 2025: 1-7 - [c17]Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan:
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. DAC 2025: 1-7 - [c16]Ruofei Tang, Xuliang Zhu, Lei Chen, Xing Li, Xin Huang, Mingxuan Yuan, Jianliang Xu:
Maximum Fanout-Free Window Enumeration: Towards Multi-Output Sub-Structure Synthesis. DATE 2025: 1-7 - [c15]Xinyi Zhou, Xing Li, Yingzhao Lian, Yiwen Wang, Lei Chen, Mingxuan Yuan, Jianye Hao, Guangyong Chen, Pheng-Ann Heng:
Circuit Synthesis based on Hierarchical Conditional Diffusion. ACM Great Lakes Symposium on VLSI 2025: 634-640 - [c14]Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang:
Circuit Transformer: A Transformer That Preserves Logical Equivalence. ICLR 2025 - [i16]Qingyue Yang, Jie Wang, Xing Li, Zhihai Wang, Chen Chen, Lei Chen, Xianzhi Yu, Wulong Liu, Jianye Hao, Mingxuan Yuan, Bin Li:
AttentionPredictor: Temporal Pattern Matters for Efficient LLM Inference. CoRR abs/2502.04077 (2025) - [i15]Xing Li, Zeyu Xing, Yiming Li, Linping Qu, Hui-Ling Zhen, Wulong Liu, Yiwu Yao, Sinno Jialin Pan, Mingxuan Yuan:
KVTuner: Sensitivity-Aware Layer-wise Mixed Precision KV Cache Quantization for Efficient and Nearly Lossless LLM Inference. CoRR abs/2502.04420 (2025) - [i14]Hong Yankun, Xing Li, Hui-Ling Zhen, Xianzhi Yu, Wulong Liu, Mingxuan Yuan:
SVDq: 1.25-bit and 410x Key Cache Compression for LLM Attention. CoRR abs/2502.15304 (2025) - [i13]Han Wu, Yuxuan Yao, Shuqi Liu, Zehua Liu, Xiaojin Fu, Xiongwei Han, Xing Li, Hui-Ling Zhen, Tao Zhong, Mingxuan Yuan:
Unlocking Efficient Long-to-Short LLM Reasoning with Model Merging. CoRR abs/2503.20641 (2025) - [i12]Weizhe Lin, Xing Li, Zhiyuan Yang, Xiaojin Fu, Hui-Ling Zhen, Yaoyuan Wang, Xianzhi Yu, Wulong Liu, Xiaosong Li, Mingxuan Yuan:
TrimR: Verifier-based Training-Free Thinking Compression for Efficient Test-Time Scaling. CoRR abs/2505.17155 (2025) - [i11]Dimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan:
ELF: Efficient Logic Synthesis by Pruning Redundancy in Refactoring. CoRR abs/2508.08073 (2025) - [i10]Shengyin Sun, Yiming Li, Xing Li, Yingzhao Lian, Weizhe Lin, Hui-Ling Zhen, Zhiyuan Yang, Chen Chen, Xianzhi Yu, Mingxuan Yuan, Chen Ma:
Scaling Up, Speeding Up: A Benchmark of Speculative Decoding for Efficient LLM Test-Time Scaling. CoRR abs/2509.04474 (2025) - [i9]Zehua Pei, Hui-Ling Zhen, Yingchun Zhang, Zhiyuan Yang, Xing Li, Xianzhi Yu, Mingxuan Yuan, Bei Yu:
Behavioral Fingerprinting of Large Language Models. CoRR abs/2509.04504 (2025) - 2024
- [c13]Tianji Liu, Lei Chen, Xing Li, Mingxuan Yuan, Evangeline F. Y. Young:
FineMap: A Fine-grained GPU-parallel LUT Mapping Engine. ASPDAC 2024: 392-397 - [c12]Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu:
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. ICCAD 2024: 98:1-98:7 - [c11]Zhihai Wang, Lei Chen, Jie Wang, Yinqi Bai, Xing Li, Xijun Li, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, Feng Wu:
A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design. ICML 2024 - [c10]Zhihai Wang, Jie Wang, Qingyue Yang, Yinqi Bai, Xing Li, Lei Chen, Jianye Hao, Mingxuan Yuan, Bin Li, Yongdong Zhang, Feng Wu:
Towards Next-Generation Logic Synthesis: A Scalable Neural Circuit Generation Framework. NeurIPS 2024 - [i8]Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang:
Circuit Transformer: End-to-end Circuit Design by Predicting the Next Gate. CoRR abs/2403.13838 (2024) - [i7]Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang:
Logic Synthesis with Generative Deep Neural Networks. CoRR abs/2406.04699 (2024) - [i6]Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva:
MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization. CoRR abs/2409.06077 (2024) - [i5]Raika Karimi, Faezeh Faez, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva:
Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers. CoRR abs/2409.10653 (2024) - [i4]Xufeng Yao, Yiwen Wang, Xing Li, Yingzhao Lian, Ran Chen, Lei Chen, Mingxuan Yuan, Hong Xu, Bei Yu:
RTLRewriter: Methodologies for Large Models aided RTL Code Optimization. CoRR abs/2409.11414 (2024) - [i3]Xinyi Zhou, Xing Li, Yingzhao Lian, Yiwen Wang, Lei Chen, Mingxuan Yuan, Jianye Hao, Guangyong Chen, Pheng-Ann Heng:
SeaDAG: Semi-autoregressive Diffusion for Conditional Directed Acyclic Graph Generation. CoRR abs/2410.16119 (2024) - 2023
- [c9]Antoine Grosnit, Matthieu Zimmer, Rasul Tutunov, Xing Li, Lei Chen, Fan Yang, Mingxuan Yuan, Haitham Bou-Ammar:
Lightweight Structural Choices Operator for Technology Mapping. DAC 2023: 1-6 - [c8]Xuliang Zhu, Ruofei Tang, Lei Chen, Xing Li, Xin Huang, Mingxuan Yuan, Weihua Sheng, Jianliang Xu:
A Database Dependent Framework for K-Input Maximum Fanout-Free Window Rewriting. DAC 2023: 1-6 - [c7]Xinshi Zang, Lei Chen, Xing Li, Wilson W. K. Thong, Weihua Sheng, Evangeline F. Y. Young, Martin D. F. Wong:
CPP: A Multi-Level Circuit Partitioning Predictor for Hardware Verification Systems. ACM Great Lakes Symposium on VLSI 2023: 357-361 - [c6]Xing Li, Lei Chen, Jiantang Zhang, Shuang Wen, Weihua Sheng, Yu Huang, Mingxuan Yuan:
EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning. ICCAD 2023: 1-9 - [c5]Peiyu Wang, Anqi Lu, Xing Li, Junjie Ye, Lei Chen, Mingxuan Yuan, Jianye Hao, Junchi Yan:
EasyMap: Improving Technology Mapping via Exploration-Enhanced Heuristics and Adaptive Sequencing. ICCAD 2023: 1-9 - [c4]Junfeng Liu, Liwei Ni, Xingquan Li, Min Zhou, Lei Chen, Xing Li, Qinghua Zhao, Shuai Ma:
AiMap: Learning to Improve Technology Mapping for ASICs via Delay Prediction. ICCD 2023: 344-347 - [c3]Yiyuan Yang, Rongshang Li, Qiquan Shi, Xijun Li, Gang Hu, Xing Li, Mingxuan Yuan:
SGDP: A Stream-Graph Neural Network Based Data Prefetcher. IJCNN 2023: 1-8 - [i2]Yiyuan Yang, Rongshang Li, Qiquan Shi, Xijun Li, Gang Hu, Xing Li, Mingxuan Yuan:
SGDP: A Stream-Graph Neural Network Based Data Prefetcher. CoRR abs/2304.03864 (2023) - [i1]Zhihai Wang, Lei Chen, Jie Wang, Xing Li, Yinqi Bai, Xijun Li, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, Feng Wu:
A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design. CoRR abs/2309.03208 (2023) - 2022
- [c2]Xing Li, Lei Chen, Fan Yang, Mingxuan Yuan, Hongli Yan, Yupeng Wan:
HIMap: a heuristic and iterative logic synthesis approach. DAC 2022: 415-420 - 2021
- [c1]Xing Li, Qiquan Shi, Gang Hu, Lei Chen, Hui Mao, Yiyuan Yang, Mingxuan Yuan, Jia Zeng, Zhuo Cheng:
Block Access Pattern Discovery via Compressed Full Tensor Transformer. CIKM 2021: 957-966
Coauthor Index
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