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Dingxin Xu
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2020 – today
- 2024
- [j6]Xiwen Qin, Xing Ji, Siqi Zhang, Dingxin Xu:
A credit scoring ensemble model incorporating fuzzy clustering particle swarm optimization algorithm. J. Intell. Fuzzy Syst. 46(2): 5359-5376 (2024) - [j5]Yuncheng Zhang
, Zheng Sun
, Bangan Liu
, Junjun Qiu
, Dingxin Xu
, Yi Zhang
, Xi Fu
, Dongwon You, Hongye Huang
, Waleed Madany
, Ashbir Aviat Fadila
, Zezheng Liu
, Wenqian Wang, Yuang Xiong
, Atsushi Shirane, Kenichi Okada
:
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Hybrid FIR Filter. IEEE J. Solid State Circuits 59(4): 993-1005 (2024) - [c7]Dingxin Xu, Zezheng Liu, Yifeng Kuai, Hongye Huang, Yuncheng Zhang, Zheng Sun, Bangan Liu, Wenqian Wang, Yuang Xiong, Junjun Qiu, Waleed Madany, Yi Zhang, Ashbir Aviat Fadila, Atsushi Shirane, Kenichi Okada:
10.3 A 7GHz Digital PLL with Cascaded Fractional Divider and Pseudo-Differential DTC Achieving -62.1dBc Fractional Spur and 143.7fs Integrated Jitter. ISSCC 2024: 192-194 - 2023
- [j4]Xiwen Qin
, Dingxin Xu
, Xiaogang Dong, Xueteng Cui
, Siqi Zhang:
EEG signal classification based on improved variational mode decomposition and deep forest. Biomed. Signal Process. Control. 83: 104644 (2023) - [c6]Dingxin Xu, Yuncheng Zhang, Hongye Huang
, Zheng Sun, Bangan Liu, Ashbir Aviat Fadila, Junjun Qiu, Zezheng Liu, Wenqian Wang, Yuang Xiong, Waleed Madany
, Atsushi Shirane, Kenichi Okada:
A 6.5-to-8GHz Cascaded Dual-Fractional-N Digital PLL Achieving -63.7dBc Fractional Spurs with 50MHz Reference. CICC 2023: 1-2 - [c5]Junjun Qiu, Wenqian Wang, Zheng Sun, Bangan Liu, Yuncheng Zhang, Dingxin Xu, Hongye Huang
, Ashbir Aviat Fadila, Zezheng Liu, Waleed Madany
, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A 32kHz-Reference 2.4GHz Fractional-N Nonuniform Oversampling PLL with Gain-Boosted PD and Loop-Gain Calibration. ISSCC 2023: 80-81 - [c4]Yuncheng Zhang, Zheng Sun, Bangan Liu, Junjun Qiu, Dingxin Xu, Yi Zhang, Xi Fu
, Dongwon You, Hongye Huang, Waleed Madany
, Ashbir Aviat Fadila, Zezheng Liu, Wenqian Wang, Yuang Xiong, Atsushi Shirane, Kenichi Okada:
A Time-Mode-Modulation Digital Quadrature Power Amplifier Based on 1-bit Delta-Sigma Modulator and Transformer Combined FIR FIlter. VLSI Technology and Circuits 2023: 1-2 - 2021
- [j3]Junjun Qiu
, Zheng Sun
, Bangan Liu
, Wenqian Wang, Dingxin Xu
, Hans Herdian
, Hongye Huang
, Yuncheng Zhang
, Yun Wang
, Jian Pang
, Hanli Liu
, Masaya Miyahara, Atsushi Shirane
, Kenichi Okada
:
A 32-kHz-Reference 2.4-GHz Fractional-N Oversampling PLL With 200-kHz Loop Bandwidth. IEEE J. Solid State Circuits 56(12): 3741-3755 (2021) - [j2]Zheng Sun
, Hanli Liu
, Hongye Huang
, Dexian Tang, Dingxin Xu, Tohru Kaneko, Zheng Li, Jian Pang
, Rui Wu
, Wei Deng
, Atsushi Shirane
, Kenichi Okada
:
A 0.85mm2 BLE Transceiver Using an On-Chip Harmonic-Suppressed RFIO Circuitry With T/R Switch. IEEE Trans. Circuits Syst. I Regul. Pap. 68(1): 196-209 (2021) - [c3]Zheng Sun, Dingxin Xu, Junjun Qiu, Zezheng Liu, Yuncheng Zhang
, Hongye Huang
, Hanli Liu, Bangan Liu, Zheng Li, Jian Pang, Atsushi Shirane, Kenichi Okada:
A 0.25 mm2 BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration. ESSCIRC 2021: 499-502 - [c2]Junjun Qiu, Zheng Sun, Bangan Liu, Wenqian Wang, Dingxin Xu, Hans Herdian, Hongye Huang, Yuncheng Zhang
, Yun Wang, Atsushi Shirane
, Kenichi Okada:
32.7 A 32kHz-Reference 2.4GHz Fractional-N Oversampling PLL with 200kHz Loop Bandwidth. ISSCC 2021: 454-456 - 2020
- [j1]Zheng Sun, Dingxin Xu, Hongye Huang
, Zheng Li, Hanli Liu, Bangan Liu, Jian Pang, Teruki Someya, Atsushi Shirane
, Kenichi Okada
:
A Compact TF-Based LC-VCO with Ultra-Low-Power Operation and Supply Pushing Reduction for IoT Applications. IEICE Trans. Electron. 103-C(10): 505-513 (2020)
2010 – 2019
- 2019
- [c1]Zheng Sun, Hanli Liu, Dingxin Xu, Hongye Huang
, Bangan Liu, Zheng Li, Jian Pang, Teruki Someya, Atsushi Shirane:
A 78 fs RMS Jitter Injection-Locked Clock Multiplier Using Transformer-Based Ultra-Low-Power VCO. ESSCIRC 2019: 101-104
Coauthor Index
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last updated on 2024-08-05 21:16 CEST by the dblp team
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