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2020 – today
- 2024
[c8]Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli:
Technology-Aware Logic Synthesis for Superconducting Electronics. DATE 2024: 1-6- 2023
- [j2]Siang-Yun Lee
, Giovanni De Micheli:
Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 3958-3971 (2023) - [i4]Hanyu Wang, Siang-Yun Lee, Giovanni De Micheli:
AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions. CoRR abs/2311.14721 (2023) - 2022
- [j1]Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8): 2573-2586 (2022) - [c7]Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli:
Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ASP-DAC 2022: 395-402 - [c6]Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Beyond local optimality of buffer and splitter insertion for AQFP circuits. DAC 2022: 445-450 - [c5]Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli:
Majority-based Design Flow for AQFP Superconducting Family. DATE 2022: 34-39 - [i3]Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications. CoRR abs/2207.13487 (2022) - 2021
- [c4]Eleonora Testa, Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits. ASP-DAC 2021: 779-785 - [c3]Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition. DDECS 2021: 105-110 - [i2]Siang-Yun Lee, Heinz Riener, Giovanni De Micheli:
Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits. CoRR abs/2109.00291 (2021) - 2020
- [i1]Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli:
Simulation-Guided Boolean Resubstitution. CoRR abs/2007.02579 (2020)
2010 – 2019
- 2019
- [c2]Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Searching Parallel Separating Hyperplanes for Effective Compression of Threshold Logic Networks. ICCAD 2019: 1-8 - 2018
- [c1]Siang-Yun Lee, Nian-Ze Lee, Jie-Hong R. Jiang:
Canonicalization of threshold logic representation and its applications. ICCAD 2018: 85
Coauthor Index
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