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Journal Articles
- 2023
[j6]Lucas Bragança
, Michael Canesche, Jeronimo Costa Penha, Josué Campos, José Augusto Miranda Nacif, Ricardo S. Ferreira:
Fast flow cloud: A stream dataflow framework for cloud FPGA accelerator overlays at runtime. Concurr. Comput. Pract. Exp. 35(17) (2023)- [j5]Jeronimo Costa Penha, Lucas Bragança, Michael Canesche, Dener Ribeiro, José Augusto Miranda Nacif, Ricardo S. Ferreira:
Gene regulatory accelerators on cloud FPGA. Concurr. Comput. Pract. Exp. 35(24) (2023) - 2021
- [j4]Danilo Damião Almeida, Lucas Bragança, Frank Sill Torres, Ricardo Ferreira, José Augusto Miranda Nacif:
HAMBug: A Hybrid CPU-FPGA System to Detect Race Conditions. IEEE Trans. Circuits Syst. II Express Briefs 68(9): 3158-3162 (2021) - 2020
- [j3]Racyus D. G. Pacífico, Lucas B. da Silva, Gerferson R. Coelho, Pablo G. Silva, Alex Borges Vieira, Marcos Augusto M. Vieira, Ítalo S. Cunha, Luiz Filipe M. Vieira, José Augusto Miranda Nacif:
BloomTime: space-efficient stateful tracking of time-dependent network performance metrics. Telecommun. Syst. 74(2): 201-223 (2020) - 2019
- [j2]Jeronimo Costa Penha, Lucas B. da Silva, Jansen Silva, Kristtopher Coelho, Hector P. Baranda, José Augusto Miranda Nacif, Ricardo Ferreira:
ADD: Accelerator Design and Deploy - A tool for FPGA high-performance dataflow computing. Concurr. Comput. Pract. Exp. 31(18) (2019) - [j1]Lucas Bragança da Silva, Ricardo S. Ferreira, Michael Canesche, Marcelo M. Menezes, Maria D. Vieira, Jeronimo Costa Penha, Peter Jamieson, José Augusto Miranda Nacif:
READY: A Fine-Grained Multithreading Overlay Framework for Modern CPU-FPGA Dataflow Applications. ACM Trans. Embed. Comput. Syst. 18(5s): 56:1-56:20 (2019)
Conference and Workshop Papers
- 2021
- [c10]Michael Canesche, Lucas Bragança, Omar Paranaiba Vilela Neto, José Augusto Miranda Nacif, Ricardo S. Ferreira:
Google Colab CAD4U: Hands-On Cloud Laboratories for Digital Design. ISCAS 2021: 1-5 - [c9]Maria D. Vieira, Michael Canesche, Lucas Bragança, Josué Campos, Mateus Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
RESHAPE: A Run-Time Dataflow Hardware-Based Mapping for CGRA Overlays. ISCAS 2021: 1-5 - [c8]Lucas Bragança, Michael Canesche, Jeronimo Costa Penha, Westerley Carvalho, Giovanni Comarela, José Augusto Miranda Nacif, Ricardo S. Ferreira:
An Open Source Custom K-means Generator for AWS Cloud FPGA Accelerators. SBESC 2021: 1-8 - 2020
- [c7]Westerley Carvalho, Michael Canesche, Lucas Reis, Frank Sill Torres, Lucas B. da Silva, Peter Jamieson, José Augusto Miranda Nacif, Ricardo S. Ferreira:
A Design Exploration of Scalable Mesh-based Fully Pipelined Accelerators. FPT 2020: 233-236 - 2018
- [c6]Lucas Bragança, Fredy A. M. Alves, Jeronimo Costa Penha, Gabriel T. P. Coimbra, Ricardo Ferreira, José Augusto Miranda Nacif:
Simplifying HW/SW integration to deploy multiple accelerators for CPU-FPGA heterogeneous platforms. SAMOS 2018: 97-104 - [c5]Fredy A. M. Alves, Peter Jamieson, Lucas Bragança, Ricardo Ferreira, José Augusto Miranda Nacif:
Lessons learned on which applications benefit when implemented on CPU-FPGA heterogeneous system. SAMOS 2018: 150-156 - [c4]Pedro Caldeira, Jeronimo Costa Penha, Lucas Bragança, Ricardo Ferreira, José Augusto Miranda Nacif, Renato Ferreira, Fernando Magno Quintão Pereira:
From Java to FPGA: An Experience with the Intel HARP System. SBAC-PAD 2018: 17-24 - [c3]Jeronimo Costa Penha, Lucas Bragança, Kristtopher Coelho, Michael Canesche, Jansen Silva, Giovanni Comarela, José Augusto Miranda Nacif, Ricardo Ferreira:
A GPU/FPGA-Based K-Means Clustering Using a Parameterized Code Generator. WSCAD 2018: 61-69 - 2017
- [c2]Fredy Augusto M. Alves, Peter Jamieson, Lucas B. da Silva, Ricardo S. Ferreira, José Augusto Miranda Nacif:
Designing a collision detection accelerator on a heterogeneous CPU-FPGA platform. ReConFig 2017: 1-6 - [c1]Lucas B. da Silva, Danilo Damião Almeida, José Augusto Miranda Nacif, Ismael Sanchez-Osorio, Carlos A. Hernandez-Martinez, Ricardo Ferreira:
Exploring the dynamics of large-scale gene regulatory networks using hardware acceleration on a heterogeneous CPU-FPGA platform. ReConFig 2017: 1-7
Coauthor Index
aka: José Augusto Miranda Nacif
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